sensor_epsonV340.h
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1 //==============================================================================
2 //
3 // sensor_epsonV340.h - Epson V340 sensor specific definitions
4 //
5 //
6 // THE SOFTWARE IS RELEASED INTO THE PUBLIC DOMAIN.
7 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
8 // INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT,
9 // SECURITY, SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
10 // SHALL EPSON BE LIABLE FOR ANY LOSS, DAMAGE OR CLAIM, ARISING FROM OR IN CONNECTION
11 // WITH THE SOFTWARE OR THE USE OF THE SOFTWARE.
12 //
13 //==============================================================================
14 #ifndef EPSONV340_H_
15 #define EPSONV340_H_
16 #include<math.h>
17 #include<stdio.h>
18 
19 #define TRUE 1
20 #define FALSE 0
21 
22 #define EPSON_ACCL_SF (.180)
23 #define EPSON_GYRO_SF (.015)
24 
25 // V340 sensor read output is 16-bit only
26 // Define length in 16-bit words
27 // And the output packet contents may contain data in addition to gyro & accel
28 // # Bytes = ND_FLAG(2) + Temp(2) + Gyro(6) + Accel(6) + GPIO(2) + Count(2)
29 // Do not count Header/Delimiter byte which is discarded by low-level function
30 #define SENSOR_READ_LEN 10
31 // This is defined in bytes and includes Header/Delimiter byte
32 #define BURSTLEN 22
33 
34 /* -- Commands --
35  - ADDR_ address byte of transfer to select the register to access
36  - VAL_ data byte of transfer to write to the register selected
37 
38  - All accesses are 16 bit transfers
39  - For SPI IF:
40  - For SPI write accesses - 8-bit address with msb=1b (can be even or odd) + 8-bit write data
41  - No response
42  - For SPI read accesses - 8-bit address with msb=0b(even only) + 8-bit dummy data
43  - Response is transferred on MOSI on next SPI access
44  - Return value is 16-bit read data (high byte + low byte)
45  - For UART IF:
46  - For UART write accesses - 8-bit address with msb=1b(can be even or odd) + 8-bit write data + Delimiter Byte
47  - No response
48  - For UART read accesses - 8-bit address with msb=0b(even only) + 8-bit dummy data + Delimiter Byte
49  - Response is transferred immediately
50  - Return value consists of Register Read Address + 16-bit read data (high byte + low byte) + Delimiter Byte
51 
52  - NOTE: G354/G364/G352/G362/G320 have Register Address Maps that depend on the WINDOW_ID (page) */
53 
54 
55 // WINDOW_ID 0
56 #define ADDR_FLAG 0x00 // FLAG(ND/EA) (W0)
57 #define ADDR_TEMP_LOW 0x02 // TEMPC Byte0 (W0)
58 #define ADDR_TEMP_HIGH 0x02 // TEMPC Byte1 (W0)
59 #define ADDR_XGYRO_HIGH 0x04 // XGYRO Byte0 (W0)
60 #define ADDR_XGYRO_LOW 0x04 // XGYRO Byte1 (W0)
61 #define ADDR_YGYRO_HIGH 0x06 // YGYRO Byte0 (W0)
62 #define ADDR_YGYRO_LOW 0x06 // YGYRO Byte1 (W0)
63 #define ADDR_ZGYRO_HIGH 0x08 // ZGYRO Byte0 (W0)
64 #define ADDR_ZGYRO_LOW 0x08 // ZGYRO Byte1 (W0)
65 #define ADDR_XACCL_HIGH 0x0A // XACCL Byte0 (W0)
66 #define ADDR_XACCL_LOW 0x0A // XACCL Byte1 (W0)
67 #define ADDR_YACCL_HIGH 0x0C // YACCL Byte0 (W0)
68 #define ADDR_YACCL_LOW 0x0C // YACCL Byte1 (W0)
69 #define ADDR_ZACCL_HIGH 0x0E // ZACCL Byte0 (W0)
70 #define ADDR_ZACCL_LOW 0x0E // ZACCL Byte1 (W0)
71 #define ADDR_GPIO 0x10 // GPIO (W0)
72 #define ADDR_COUNT 0x12 // COUNT (W0)
73 #define ADDR_SIG_CTRL_LO 0x32 // SIG_CTRL Byte0 (W0)
74 #define ADDR_SIG_CTRL_HI 0x33 // SIG_CTRL Byte1 (W0)
75 #define ADDR_MSC_CTRL_LO 0x34 // MSC_CTRL Byte0 (W0)
76 #define ADDR_MSC_CTRL_HI 0x35 // MSC_CTRL Byte1 (W0)
77 #define ADDR_SMPL_CTRL_LO 0x36 // SMPL_CTRL Byte0 (W0)
78 #define ADDR_SMPL_CTRL_HI 0x37 // SMPL_CTRL Byte1 (W0)
79 #define ADDR_FILTER_CTRL_LO 0x38 // FILTER_CTRL Byte0 (W0)
80 #define ADDR_MODE_CTRL_LO 0x38 // MODE_CTRL Byte0 (W0)
81 #define ADDR_MODE_CTRL_HI 0x39 // MODE_CTRL Byte1 (W0)
82 #define ADDR_UART_CTRL_LO 0x3A // UART_CTRL Byte0 (W0)
83 #define ADDR_UART_CTRL_HI 0x3B // UART_CTRL Byte1 (W0)
84 #define ADDR_DIAG_STAT 0x3C // DIAG_STAT Byte0 (W0)
85 #define ADDR_GLOB_CMD_LO 0x3E // GLOB_CMD Byte0 (W0)
86 #define ADDR_GLOB_CMD_HI 0x3F // GLOB_CMD Byte1 (W0)
87 #define ADDR_COUNT_CTRL_LO 0x50 // COUNT_CTRL Byte0 (W0)
88 
89 #define ADDR_PROD_ID1 0x6A // PROD_ID1(W0)
90 #define ADDR_PROD_ID2 0x6C // PROD_ID2(W0)
91 #define ADDR_PROD_ID3 0x6E // PROD_ID3(W0)
92 #define ADDR_PROD_ID4 0x70 // PROD_ID4(W0)
93 #define ADDR_VERSION 0x72 // VERSION(W0)
94 #define ADDR_SERIAL_NUM1 0x74 // SERIAL_NUM1(W0)
95 #define ADDR_SERIAL_NUM2 0x76 // SERIAL_NUM2(W0)
96 #define ADDR_SERIAL_NUM3 0x78 // SERIAL_NUM3(W0)
97 #define ADDR_SERIAL_NUM4 0x7A // SERIAL_NUM4(W0)
98 
99 #define CMD_BURST 0x20 // BURST
100 
101 #define CMD_EN_NDFLAGS 0x7E // Write value for SIG_CTRL_HI to Enables new data (ND) flags in FLAG for Gyros, Accelerometers
102 #define CMD_EN_BRSTDATA_LO 0x03 // Write value for BURST_CTRL1_LO to enable CHKSM, and COUNT bytes in burst mode
103 #define CMD_EN_BRSTDATA_HI 0x30 // Write value for BURST_CTRL1_HI to enable GYRO, and ACCL registers in burst mode (0xB0 for FLAG as well)
104 #define CMD_WINDOW0 0x00 // Write value for WIN_CTRL to change to Window 0
105 #define CMD_WINDOW1 0x01 // Write value for WIN_CTRL to change to Window 1
106 #define CMD_DRDY_GPIO1 0x04 // Write value for MSC_CTRL_LO to enable active low DRDY on GPIO1
107 #define CMD_32BIT 0x30 // Write value for BURST_CTRL2_HI to enable 32 bit mode for gyro and accl data
108 #define CMD_BEGIN_SAMPLING 0x01 // Write value for MODE_CMD_HI to begin sampling
109 #define CMD_END_SAMPLING 0x02 // Write value for MODE_CMD_HI to stop sampling
110 #define CMD_SOFTRESET 0x80 // Write value for GLOB_CMD_LO to issue Software Reset
111 #define CMD_FLASHTEST 0x08 // Write value for MSC_CTRL_HI to issue Flashtest
112 #define CMD_SELFTEST 0x04 // Write value for MSC_CTRL_HI to issue Selftest
113 
114 // Write values for ADDR_SMPL_CTRL_HI to set Output Rate
115 #define CMD_RATE1000 0x01 // TAP>=1
116 #define CMD_RATE500 0x02 // TAP>=2
117 #define CMD_RATE250 0x03 // TAP>=4
118 #define CMD_RATE125 0x04 // TAP>=8
119 #define CMD_RATE62_5 0x05 // TAP>=16
120 #define CMD_RATE31_25 0x06 // TAP>=32
121 
122 // Write values for FILTER_CTRL_LO to set Filter
123 #define CMD_FLTAP1 0x02
124 #define CMD_FLTAP2 0x03
125 #define CMD_FLTAP4 0x04
126 #define CMD_FLTAP8 0x05
127 #define CMD_FLTAP16 0x06
128 #define CMD_FLTAP32 0x07
129 
130 // MODE STAT
131 #define VAL_SAMPLING_MODE 0x00
132 #define VAL_CONFIG_MODE 0x04
133 
134 
135 #endif /* EPSONV340_H_ */

epson_g364_imu_driver
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autogenerated on Mon Jun 10 2019 13:12:32