sensor_epsonG362.h
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1 //==============================================================================
2 //
3 // sensor_epsonG362.h - Epson G362 sensor specific definitions
4 //
5 //
6 // THE SOFTWARE IS RELEASED INTO THE PUBLIC DOMAIN.
7 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
8 // INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT,
9 // SECURITY, SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
10 // SHALL EPSON BE LIABLE FOR ANY LOSS, DAMAGE OR CLAIM, ARISING FROM OR IN CONNECTION
11 // WITH THE SOFTWARE OR THE USE OF THE SOFTWARE.
12 //
13 //==============================================================================
14 #ifndef EPSONG362_H_
15 #define EPSONG362_H_
16 #include<math.h>
17 #include<stdio.h>
18 
19 #define TRUE 1
20 #define FALSE 0
21 
22 #define EPSON_ACCL_SF (.125)
23 #define EPSON_GYRO_SF (.005)
24 
25 // G362 sensor read output is configured for 32-bit
26 // Define length in 16-bit words
27 // # Bytes = Gyro(12) + Accel(12) + Count(2) + CHKSM(2)
28 // Do not count Header/Delimiter byte which is discarded by low-level function
29 #define SENSOR_READ_LEN 14
30 // This is defined in bytes and includes Header/Delimiter byte
31 #define BURSTLEN 30
32 
33 
34 /* -- Commands --
35  - ADDR_ address byte of transfer to select the register to access
36  - VAL_ data byte of transfer to write to the register selected
37 
38  - All accesses are 16 bit transfers
39  - For SPI IF:
40  - For SPI write accesses - 8-bit address with msb=1b (can be even or odd) + 8-bit write data
41  - No response
42  - For SPI read accesses - 8-bit address with msb=0b(even only) + 8-bit dummy data
43  - Response is transferred on MOSI on next SPI access
44  - Return value is 16-bit read data (high byte + low byte)
45  - For UART IF:
46  - For UART write accesses - 8-bit address with msb=1b(can be even or odd) + 8-bit write data + Delimiter Byte
47  - No response
48  - For UART read accesses - 8-bit address with msb=0b(even only) + 8-bit dummy data + Delimiter Byte
49  - Response is transferred immediately
50  - Return value consists of Register Read Address + 16-bit read data (high byte + low byte) + Delimiter Byte
51 
52  - NOTE: G354/G364/G352/G362/G320 have Register Address Maps that depend on the WINDOW_ID (page) */
53 
54 
55 // WINDOW_ID 0
56 #define ADDR_MODE_CTRL_LO 0x02 // MODE_CTRL Byte0 (W0)
57 #define ADDR_MODE_CTRL_HI 0x03 // MODE_CTRL Byte1 (W0)
58 #define ADDR_DIAG_STAT 0x04 // DIAG_STAT Byte0 (W0)
59 #define ADDR_FLAG 0x06 // FLAG(ND/EA) (W0)
60 #define ADDR_GPIO 0x08 // GPIO (W0)
61 #define ADDR_COUNT 0x0A // COUNT (W0)
62 #define ADDR_TEMP_HIGH 0x0E // TEMPC HIGH (W0)
63 #define ADDR_TEMP_LOW 0x10 // TEMPC LOW (W0)
64 #define ADDR_XGYRO_HIGH 0x12 // XGYRO HIGH (W0)
65 #define ADDR_XGYRO_LOW 0x14 // XGYRO LOW (W0)
66 #define ADDR_YGYRO_HIGH 0x16 // YGYRO HIGH (W0)
67 #define ADDR_YGYRO_LOW 0x18 // YGYRO LOW (W0)
68 #define ADDR_ZGYRO_HIGH 0x1A // ZGYRO HIGH (W0)
69 #define ADDR_ZGYRO_LOW 0x1C // ZGYRO LOW (W0)
70 #define ADDR_XACCL_HIGH 0x1E // XACCL HIGH (W0)
71 #define ADDR_XACCL_LOW 0x20 // XACCL LOW (W0)
72 #define ADDR_YACCL_HIGH 0x22 // YACCL HIGH (W0)
73 #define ADDR_YACCL_LOW 0x24 // YACCL LOW (W0)
74 #define ADDR_ZACCL_HIGH 0x26 // ZACCL HIGH (W0)
75 #define ADDR_ZACCL_LOW 0x28 // ZACCL LOW (W0)
76 
77 // WINDOW_ID 1
78 #define ADDR_SIG_CTRL_LO 0x00 // SIG_CTRL Byte0 (W1)
79 #define ADDR_SIG_CTRL_HI 0x01 // SIG_CTRL Byte1 (W1)
80 #define ADDR_MSC_CTRL_LO 0x02 // MSC_CTRL Byte0 (W1)
81 #define ADDR_MSC_CTRL_HI 0x03 // MSC_CTRL Byte1 (W1)
82 #define ADDR_SMPL_CTRL_LO 0x04 // SMPL_CTRL Byte0 (W1)
83 #define ADDR_SMPL_CTRL_HI 0x05 // SMPL_CTRL Byte1 (W1)
84 #define ADDR_FILTER_CTRL_LO 0x06 // FILTER_CTRL Byte0 (W1)
85 #define ADDR_FILTER_CTRL_HI 0x07 // FILTER_CTRL Byte1 (W1)
86 #define ADDR_UART_CTRL_LO 0x08 // UART_CTRL Byte0 (W1)
87 #define ADDR_UART_CTRL_HI 0x09 // UART_CTRL Byte1 (W1)
88 #define ADDR_GLOB_CMD_LO 0x0A // GLOB_CMD Byte0 (W1)
89 #define ADDR_GLOB_CMD_HI 0x0B // GLOB_CMD Byte1 (W1)
90 #define ADDR_BURST_CTRL1_LO 0x0C // BURST_CTRL1 Byte0 (W1)
91 #define ADDR_BURST_CTRL1_HI 0x0D // BURST_CTRL1 Byte1 (W1)
92 #define ADDR_BURST_CTRL2_LO 0x0E // BURST_CTRL2 Byte0 (W1)
93 #define ADDR_BURST_CTRL2_HI 0x0F // BURST_CTRL2 Byte1 (W1)
94 
95 #define ADDR_PROD_ID1 0x6A // PROD_ID1(W1)
96 #define ADDR_PROD_ID2 0x6C // PROD_ID2(W1)
97 #define ADDR_PROD_ID3 0x6E // PROD_ID3(W1)
98 #define ADDR_PROD_ID4 0x70 // PROD_ID4(W1)
99 #define ADDR_VERSION 0x72 // VERSION(W1)
100 #define ADDR_SERIAL_NUM1 0x74 // SERIAL_NUM1(W1)
101 #define ADDR_SERIAL_NUM2 0x76 // SERIAL_NUM2(W1)
102 #define ADDR_SERIAL_NUM3 0x78 // SERIAL_NUM3(W1)
103 #define ADDR_SERIAL_NUM4 0x7A // SERIAL_NUM4(W1)
104 #define ADDR_WIN_CTRL 0x7E // WIN_CTRL(W0 or W1)
105 
106 #define CMD_BURST 0x80 // Write value to Issue Burst Read
107 
108 #define CMD_EN_NDFLAGS 0x7E // Write value for SIG_CTRL_HI to Enables new data (ND) flags in FLAG for Gyros, Accelerometers
109 #define CMD_EN_BRSTDATA_LO 0x03 // Write value for BURST_CTRL1_LO to enable CHKSM, and COUNT bytes in burst mode
110 #define CMD_EN_BRSTDATA_HI 0x30 // Write value for BURST_CTRL1_HI to enable GYRO, and ACCL registers in burst mode (0xB0 for FLAG as well)
111 #define CMD_WINDOW0 0x00 // Write value for WIN_CTRL to change to Window 0
112 #define CMD_WINDOW1 0x01 // Write value for WIN_CTRL to change to Window 1
113 #define CMD_RSTCNTR_DRDY 0x44 // Write value for MSC_CTRL_LO to enable EXT_SEL to Reset counter and active low DRDY on GPIO1
114 #define CMD_32BIT 0x30 // Write value for BURST_CTRL2_HI to enable 32 bit mode for gyro and accl data
115 #define CMD_BEGIN_SAMPLING 0x01 // Write value for MODE_CMD_HI to begin sampling
116 #define CMD_END_SAMPLING 0x02 // Write value for MODE_CMD_HI to stop sampling
117 #define CMD_SOFTRESET 0x80 // Write value for GLOB_CMD_LO to issue Software Reset
118 #define CMD_FLASHTEST 0x08 // Write value for MSC_CTRL_HI to issue Flashtest
119 #define CMD_SELFTEST 0x04 // Write value for MSC_CTRL_HI to issue Selftest
120 
121 // Write values for ADDR_SMPL_CTRL_HI to set Output Rate
122 #define CMD_RATE2000 0x01 // TAP>=2, Not supported for 32-bit output
123 #define CMD_RATE1000 0x02 // TAP>=4
124 #define CMD_RATE500 0x03 // TAP>=8
125 #define CMD_RATE250 0x04 // TAP>=16
126 #define CMD_RATE125 0x05 // TAP>=32
127 #define CMD_RATE62_5 0x06 // TAP>=64
128 #define CMD_RATE31_25 0x07 // TAP=128
129 
130 // Write values for FILTER_CTRL_LO to set Filter
131 #define CMD_FLTAP2 0x01
132 #define CMD_FLTAP4 0x02
133 #define CMD_FLTAP8 0x03
134 #define CMD_FLTAP16 0x04
135 #define CMD_FLTAP32 0x05
136 #define CMD_FLTAP64 0x06
137 #define CMD_FLTAP128 0x07
138 #define CMD_FIRTAP32FC50 0x08
139 #define CMD_FIRTAP32FC100 0x09
140 #define CMD_FIRTAP32FC200 0x0A
141 #define CMD_FIRTAP32FC400 0x0B
142 #define CMD_FIRTAP64FC50 0x0C
143 #define CMD_FIRTAP64FC100 0x0D
144 #define CMD_FIRTAP64FC200 0x0E
145 #define CMD_FIRTAP64FC400 0x0F
146 #define CMD_FIRTAP128FC50 0x10
147 #define CMD_FIRTAP128FC100 0x11
148 #define CMD_FIRTAP128FC200 0x12
149 #define CMD_FIRTAP128FC400 0x13
150 
151 // MODE STAT
152 #define VAL_SAMPLING_MODE 0x00
153 #define VAL_CONFIG_MODE 0x04
154 
155 #endif /* EPSONG362_H_ */

epson_g364_imu_driver
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autogenerated on Mon Jun 10 2019 13:12:32