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00030 #include <stddef.h>
00031 #include <stdio.h>
00032 #include <stdlib.h>
00033 #include <string.h>
00034
00035 #include "tm_reader.h"
00036 #include "serial_reader_imp.h"
00037 #include "tmr_utils.h"
00038
00039 #define EAPI_PREFIX "eapi://"
00040 #define EAPI_PREFIX_LEN (sizeof(EAPI_PREFIX)-1)
00041
00042 #define TMR_PREFIX "tmr://"
00043 #define TMR_PREFIX_LEN (sizeof(TMR_PREFIX)-1)
00044
00045 #define LLRP_EAPI_PREFIX "llrp+eapi://"
00046 #define LLRP_EAPI_PREFIX_LEN (sizeof(LLRP_EAPI_PREFIX)-1)
00047
00048 #define LLRP_PREFIX "llrp://"
00049 #define LLRP_PREFIX_LEN (sizeof(LLRP_PREFIX)-1)
00050
00051
00057 static void TMR_initSerialTransportTable();
00058
00059 void* do_background_receiveAutonomousReading(void * arg);
00060
00061 typedef struct TMR_SerialTransportDispatchTableData
00062 {
00063 char transportScheme[TMR_MAX_TRANSPORT_SCHEME_NAME];
00064 TMR_TransportNativeInit transportInit;
00065 }TMR_SerialTransportDispatchTableData;
00066
00067 typedef struct TMR_SerialTransportDispatchTable
00068 {
00069 TMR_SerialTransportDispatchTableData *list;
00070 uint8_t max;
00071 uint8_t len;
00072 }TMR_SerialTransportDispatchTable;
00073
00074 static bool transportTableInitialized = false;
00075 static TMR_SerialTransportDispatchTableData tdTableData[10];
00076 static TMR_SerialTransportDispatchTable tdTable;
00077
00078 static void TMR_initSerialTransportTable()
00079 {
00080 if (false == transportTableInitialized)
00081 {
00086 memset(tdTableData, 0, (sizeof(tdTableData)/sizeof(tdTableData[0])));
00087 tdTable.list = tdTableData;
00088 tdTable.max = sizeof(tdTableData)/sizeof(tdTableData[0]);
00089 tdTable.len = 0;
00090
00091
00092 {
00093 TMR_String str;
00094
00095 str.max = TMR_MAX_TRANSPORT_SCHEME_NAME;
00096 str.value = tdTable.list[tdTable.len].transportScheme;
00097 TMR_stringCopy(&str, "eapi", (int)strlen("eapi"));
00098 tdTable.list[tdTable.len].transportInit = TMR_SR_SerialTransportNativeInit;
00099 tdTable.len++;
00100
00101 str.value = tdTable.list[tdTable.len].transportScheme;
00102 TMR_stringCopy(&str, "tmr", (int)strlen("tmr"));
00103 tdTable.list[tdTable.len].transportInit = TMR_SR_SerialTransportNativeInit;
00104 tdTable.len++;
00105 }
00106 transportTableInitialized = true;
00107 }
00108 }
00109
00110 TMR_Status
00111 TMR_create_alloc(TMR_Reader **reader, const char* deviceUri)
00112 {
00113
00114 *reader = malloc(sizeof(**reader));
00115 if (NULL == *reader)
00116 return TMR_ERROR_OUT_OF_MEMORY;
00117 return TMR_create(*reader, deviceUri);
00118 }
00119
00120
00121 TMR_Status
00122 TMR_create(TMR_Reader *reader, const char* deviceUri)
00123 {
00124 TMR_Status ret;
00125
00126 ret = TMR_ERROR_INVALID;
00127
00128 #ifdef TMR_ENABLE_BACKGROUND_READS
00129
00130
00131
00132 pthread_mutex_init(&reader->backgroundLock, NULL);
00133 pthread_mutex_init(&reader->parserLock, NULL);
00134 pthread_cond_init(&reader->backgroundCond, NULL);
00135 pthread_cond_init(&reader->parserCond, NULL);
00136 pthread_cond_init(&reader->readCond, NULL);
00137 pthread_mutex_init(&reader->listenerLock, NULL);
00138 pthread_mutex_init(&reader->queue_lock, NULL);
00139 reader->readListeners = NULL;
00140 reader->authReqListeners = NULL;
00141 reader->readExceptionListeners = NULL;
00142 reader->statsListeners = NULL;
00143 reader->statusListeners = NULL;
00144 reader->readState = TMR_READ_STATE_IDLE;
00145 reader->backgroundSetup = false;
00146 reader->parserSetup = false;
00147 #endif
00148 reader->dutyCycle = false;
00149 reader->paramWait = false;
00150 reader->hasContinuousReadStarted = false;
00151
00152 #ifdef TMR_ENABLE_SERIAL_READER
00153 #ifdef TMR_ENABLE_SERIAL_TRANSPORT_NATIVE
00154 if ((strncmp(deviceUri, EAPI_PREFIX, EAPI_PREFIX_LEN) == 0)
00155 || ((strncmp(deviceUri, TMR_PREFIX, TMR_PREFIX_LEN) == 0)
00156 && *(deviceUri + TMR_PREFIX_LEN) == '/'))
00157 {
00158 uint8_t i;
00159 char *scheme;
00160 char devname[TMR_MAX_READER_NAME_LENGTH];
00161 bool scheme_exists = false;
00162
00163 TMR_initSerialTransportTable();
00164
00165 strcpy(devname, deviceUri);
00166 scheme = strtok((char *)devname, ":");
00167
00168 for (i = 0; i < tdTable.len; i++)
00169 {
00170 if (0 == strcmp(scheme, tdTable.list[i].transportScheme))
00171 {
00172 if ('e' == deviceUri[0])
00173 {
00174 scheme = (char *)deviceUri + EAPI_PREFIX_LEN;
00175 }
00176 else
00177 {
00178 scheme = (char *)deviceUri + TMR_PREFIX_LEN;
00179 }
00180 strncpy(reader->uri, deviceUri, TMR_MAX_READER_NAME_LENGTH);
00181
00182
00183 ret = tdTable.list[i].transportInit(&reader->u.serialReader.transport,
00184 &reader->u.serialReader.
00185 transportContext.nativeContext,
00186 scheme);
00187 if (TMR_SUCCESS != ret)
00188 {
00189 return ret;
00190 }
00191
00192 scheme_exists = true;
00193 break;
00194 }
00195 }
00196
00197 if (false == scheme_exists)
00198 {
00199
00200 return TMR_ERROR_INVALID;
00201 }
00202 return TMR_SR_SerialReader_init(reader);
00203 }
00204 else
00205 #endif
00206 if ((strncmp(deviceUri, LLRP_PREFIX, LLRP_PREFIX_LEN) == 0)
00207 || (strncmp(deviceUri, TMR_PREFIX, TMR_PREFIX_LEN) == 0))
00208 {
00209 #ifdef TMR_ENABLE_LLRP_READER
00210 const char *host, *port;
00211 char hostCopy[256];
00212
00213 if ('t' == deviceUri[0])
00214 {
00215 host = deviceUri + TMR_PREFIX_LEN;
00216 }
00217 else
00218 {
00219 host = deviceUri + LLRP_PREFIX_LEN;
00220 }
00221 port = strchr(host, ':');
00222 strcpy(hostCopy, host);
00223 if (port == NULL)
00224 {
00225 char *slash;
00226 reader->u.llrpReader.portNum = TMR_LLRP_READER_DEFAULT_PORT;
00227 slash = strchr(hostCopy, '/');
00228 if (slash)
00229 {
00230 *slash = '\0';
00231 }
00232 }
00233 else
00234 {
00235 reader->u.llrpReader.portNum = atoi(port + 1);
00236 hostCopy[port - host] = '\0';
00237 }
00238
00239 strncpy(reader->uri, hostCopy, TMR_MAX_READER_NAME_LENGTH);
00240 return TMR_LLRP_LlrpReader_init(reader);
00241
00242 #else
00243 return TMR_ERROR_UNSUPPORTED_READER_TYPE;
00244 #endif
00245 }
00246 else
00247 {
00252 uint8_t i;
00253 char* scheme;
00254 bool scheme_exists = false;
00255
00256 scheme = strtok((char *)deviceUri, ":");
00257
00258 for (i = 0; i < tdTable.len; i++)
00259 {
00260 if (0 == strcmp(scheme, tdTable.list[i].transportScheme))
00261 {
00262 deviceUri += strlen(scheme) + 2;
00263 strncpy(reader->uri, deviceUri, TMR_MAX_READER_NAME_LENGTH);
00264
00265
00266 ret = tdTable.list[i].transportInit(&reader->u.serialReader.transport,
00267 &reader->u.serialReader.
00268 transportContext.nativeContext,
00269 reader->uri);
00270 if (TMR_SUCCESS != ret)
00271 {
00272 return ret;
00273 }
00274
00275 scheme_exists = true;
00276 break;
00277 }
00278 }
00279
00280 if (false == scheme_exists)
00281 {
00282
00283 return TMR_ERROR_INVALID;
00284 }
00285 return TMR_SR_SerialReader_init(reader);
00286 }
00287
00288
00289 #else
00290
00291 return TMR_ERROR_INVALID;
00292 #endif
00293 }
00294
00295 TMR_Status
00296 TMR_reader_init_internal(struct TMR_Reader *reader)
00297 {
00298 reader->connected = false;
00299 reader->pSupportsResetStats = NULL;
00300 reader->transportListeners = NULL;
00301
00302
00303 TMR_RP_init_simple(&reader->readParams.defaultReadPlan, 0, NULL,
00304 TMR_TAG_PROTOCOL_GEN2, 1);
00305 reader->readParams.readPlan = &reader->readParams.defaultReadPlan;
00306 #ifdef TMR_ENABLE_BACKGROUND_READS
00307 reader->readParams.asyncOnTime = 250;
00308 reader->readParams.asyncOffTime = 0;
00309 #if 0
00310 pthread_mutex_init(&reader->backgroundLock, NULL);
00311 pthread_mutex_init(&reader->parserLock, NULL);
00312 pthread_cond_init(&reader->backgroundCond, NULL);
00313 pthread_cond_init(&reader->parserCond, NULL);
00314 pthread_cond_init(&reader->readCond, NULL);
00315 pthread_mutex_init(&reader->listenerLock, NULL);
00316 pthread_mutex_init(&reader->queue_lock, NULL);
00317 reader->readListeners = NULL;
00318 reader->authReqListeners = NULL;
00319 reader->readExceptionListeners = NULL;
00320 reader->statsListeners = NULL;
00321 reader->statusListeners = NULL;
00322 reader->readState = TMR_READ_STATE_IDLE;
00323 reader->backgroundSetup = false;
00324 reader->parserSetup = false;
00325 #endif
00326 reader->backgroundEnabled = false;
00327 reader->trueAsyncflag = false;
00328 reader->parserEnabled = false;
00329 reader->tagQueueHead = NULL;
00330 reader->tagQueueTail = NULL;
00331 reader->isStatusResponse = false;
00332 reader->statsFlag = TMR_READER_STATS_FLAG_NONE;
00333 reader->streamStats = TMR_SR_STATUS_NONE;
00334 reader->finishedReading = true;
00335 #endif
00336 reader->continuousReading = false;
00337 reader->searchStatus = false;
00338 reader->fastSearch = false;
00339 reader->backgroundThreadCancel = false;
00340 reader->isStopNTags = false;
00341 reader->numberOfTagsToRead = 0;
00342 reader->userMetadataFlag = TMR_TRD_METADATA_FLAG_ALL;
00343 reader->portmask = 0;
00344
00345 return TMR_SUCCESS;
00346 }
00347
00348 TMR_Status
00349 TMR_setSerialTransport(char* scheme, TMR_TransportNativeInit nativeInit)
00350 {
00351 bool scheme_exists = false;
00352 uint8_t i;
00353
00354 TMR_initSerialTransportTable();
00355
00356 if ((0 == strcmp("llrp", scheme))
00357 || (0 == strcmp("llrp", scheme)))
00358 {
00363 return TMR_ERROR_UNSUPPORTED;
00364 }
00365
00366 for (i = 0; i < tdTable.len; i++)
00367 {
00368 if (0 == strcmp(scheme, tdTable.list[i].transportScheme))
00369 {
00370
00371 if (NULL != nativeInit)
00372 {
00373 tdTable.list[i].transportInit = nativeInit;
00374 }
00375 scheme_exists = true;
00376 break;
00377 }
00378 }
00379
00380 if (false == scheme_exists)
00381 {
00382
00383 TMR_String str;
00384
00385
00386 str.max = TMR_MAX_TRANSPORT_SCHEME_NAME;
00387 str.value = tdTable.list[tdTable.len].transportScheme;
00388 TMR_stringCopy(&str, scheme, (int)strlen(scheme));
00389 tdTable.list[tdTable.len].transportInit = nativeInit;
00390 tdTable.len++;
00391 }
00392 return TMR_SUCCESS;
00393 }
00394 #ifdef TMR_ENABLE_API_SIDE_DEDUPLICATION
00395
00396 static int
00397 TMR_findDupTag(TMR_Reader *reader,
00398 TMR_TagReadData* newRead,
00399 TMR_TagReadData oldReads[], int32_t oldLength,
00400 bool uniqueByAntenna, bool uniqueByData, bool uniqueByProtocol)
00401 {
00402 int i;
00403
00404 for (i=0; i<oldLength; i++)
00405 {
00406 TMR_TagReadData* oldRead = &oldReads[i];
00407 TMR_TagData* oldTag = &oldRead->tag;
00408 TMR_TagData* newTag = &newRead->tag;
00409
00410 if ((oldTag->epcByteCount != newTag->epcByteCount) ||
00411 (0 != memcmp(oldTag->epc, newTag->epc,
00412 (oldTag->epcByteCount)*sizeof(uint8_t))))
00413 {
00414 continue;
00415 }
00416 if (uniqueByAntenna)
00417 {
00418 if (oldRead->antenna != newRead->antenna)
00419 {
00420 continue;
00421 }
00422 }
00423 if (uniqueByData)
00424 {
00425 if ((oldRead->data.len != newRead->data.len) ||
00426 (0 != memcmp(oldRead->data.list, newRead->data.list,
00427 (oldRead->data.len)*sizeof(uint8_t))))
00428 {
00429 continue;
00430 }
00431 }
00432 if (uniqueByProtocol)
00433 {
00434 if (oldRead->tag.protocol != newRead->tag.protocol)
00435 {
00436 continue;
00437 }
00438 }
00439
00440 break;
00441 }
00442
00443 return (i < oldLength) ? i : -1;
00444 }
00445
00446 static void
00447 TMR_updateDupTag(TMR_Reader* reader,
00448 TMR_TagReadData* oldRead, TMR_TagReadData* newRead,
00449 bool highestRssi)
00450 {
00451 oldRead->readCount += newRead->readCount;
00452
00453 if (highestRssi)
00454 {
00455 if (newRead->rssi > oldRead->rssi)
00456 {
00457 uint32_t saveCount = oldRead->readCount;
00458
00459 memcpy(oldRead, newRead, sizeof(TMR_TagReadData));
00460
00461
00462
00463 oldRead->readCount = saveCount;
00464 }
00465 }
00466 }
00467
00468 #endif
00469
00470 TMR_Status
00471 TMR_readIntoArray(struct TMR_Reader *reader, uint32_t timeoutMs,
00472 int32_t *tagCount, TMR_TagReadData *result[])
00473 {
00474 int32_t tagsRead, count, alloc;
00475 TMR_TagReadData *results;
00476 TMR_Status ret;
00477 uint32_t startHi, startLo, nowHi, nowLo;
00478 #ifdef TMR_ENABLE_API_SIDE_DEDUPLICATION
00479 bool uniqueByAntenna, uniqueByData, recordHighestRssi, uniqueByProtocol;
00480 #endif
00481
00482 #ifdef TMR_ENABLE_API_SIDE_DEDUPLICATION
00483 {
00484 bool bval;
00485
00486 ret = TMR_paramGet(reader, TMR_PARAM_TAGREADDATA_UNIQUEBYANTENNA, &bval);
00487 if (TMR_ERROR_NOT_FOUND == ret) { bval = false; }
00488 else if (TMR_SUCCESS != ret) { return ret; }
00489 uniqueByAntenna = bval;
00490
00491 ret = TMR_paramGet(reader, TMR_PARAM_TAGREADDATA_UNIQUEBYDATA, &bval);
00492 if (TMR_ERROR_NOT_FOUND == ret) { bval = false; }
00493 else if (TMR_SUCCESS != ret) { return ret; }
00494 uniqueByData = bval;
00495
00496 ret = TMR_paramGet(reader, TMR_PARAM_TAGREADDATA_UNIQUEBYPROTOCOL, &bval);
00497 if (TMR_ERROR_NOT_FOUND == ret) { bval = false; }
00498 else if (TMR_SUCCESS != ret) { return ret; }
00499 uniqueByProtocol = bval;
00500
00501 ret = TMR_paramGet(reader, TMR_PARAM_TAGREADDATA_RECORDHIGHESTRSSI, &bval);
00502 if (TMR_ERROR_NOT_FOUND == ret) { bval = false; }
00503 else if (TMR_SUCCESS != ret) { return ret; }
00504 recordHighestRssi = bval;
00505 }
00506 #endif
00507
00508 tagsRead = 0;
00509 alloc = 0;
00510 results = NULL;
00511
00512 tm_gettime_consistent(&startHi, &startLo);
00513 do
00514 {
00515
00516 ret = TMR_read(reader, timeoutMs, &count);
00517 if ((TMR_SUCCESS != ret) && (TMR_ERROR_TAG_ID_BUFFER_FULL != ret))
00518 {
00519 goto out;
00520 }
00521
00522 if (0 == count)
00523 {
00524 goto out;
00525 }
00526 else if (-1 == count)
00527 {
00528 alloc += 4;
00529 }
00530 else
00531 {
00532 alloc += count;
00533 }
00534
00535 {
00536 TMR_TagReadData *newResults;
00537 newResults = realloc(results, alloc * sizeof(*results));
00538 if (NULL == newResults)
00539 {
00540 ret = TMR_ERROR_OUT_OF_MEMORY;
00541 goto out;
00542 }
00543 results = newResults;
00544 }
00545 while (TMR_SUCCESS == TMR_hasMoreTags(reader))
00546 {
00547 if (tagsRead == alloc)
00548 {
00549 TMR_TagReadData *newResults;
00550 alloc *= 2;
00551 newResults = realloc(results, alloc * sizeof(*results));
00552 if (NULL == newResults)
00553 {
00554 ret = TMR_ERROR_OUT_OF_MEMORY;
00555 goto out;
00556 }
00557 results = newResults;
00558 }
00559 TMR_TRD_init(&results[tagsRead]);
00560 ret = TMR_getNextTag(reader, &results[tagsRead]);
00561 if (TMR_SUCCESS != ret)
00562 {
00563 goto out;
00564 }
00565 #ifndef TMR_ENABLE_API_SIDE_DEDUPLICATION
00566 tagsRead++;
00567 #else
00568
00569
00570
00571
00572 if (true == reader->u.serialReader.enableReadFiltering)
00573 {
00574 TMR_TagReadData* last = &results[tagsRead];
00575 int dupIndex = TMR_findDupTag(reader, last, results, tagsRead,
00576 uniqueByAntenna, uniqueByData, uniqueByProtocol);
00577 if (-1 == dupIndex)
00578 {
00579 tagsRead++;
00580 }
00581 else
00582 {
00583 TMR_updateDupTag(reader, &results[dupIndex], last,
00584 recordHighestRssi);
00585 }
00586 }
00587 else
00588 {
00589 tagsRead++;
00590 }
00591 #endif
00592 }
00593
00594 tm_gettime_consistent(&nowHi, &nowLo);
00595 }
00596 while (tm_time_subtract(nowLo, startLo) < timeoutMs);
00597
00598 out:
00599 if (NULL != tagCount)
00600 *tagCount = tagsRead;
00601 *result = results;
00602 return ret;
00603 }
00604
00605 TMR_Status
00606 validateReadPlan(TMR_Reader *reader, TMR_ReadPlan *plan,
00607 TMR_AntennaMapList *txRxMap, uint32_t protocols)
00608 {
00609 TMR_Status ret;
00610 int i, j;
00611
00612 if (TMR_READ_PLAN_TYPE_MULTI == plan->type)
00613 {
00614 plan->u.multi.totalWeight = 0;
00615 for (i = 0; i < plan->u.multi.planCount; i++)
00616 {
00617 ret = validateReadPlan(reader, plan->u.multi.plans[i], txRxMap, protocols);
00618 if (TMR_SUCCESS != ret)
00619 {
00620 return ret;
00621 }
00622 plan->u.multi.totalWeight += plan->u.multi.plans[i]->weight;
00623 }
00624 }
00625 else if (TMR_READ_PLAN_TYPE_SIMPLE == plan->type)
00626 {
00627 if (0 == ((1 << (plan->u.simple.protocol - 1)) & protocols))
00628 {
00629 return TMR_ERROR_INVALID_PROTOCOL_SPECIFIED;
00630 }
00631 for (i = 0 ; i < plan->u.simple.antennas.len; i++)
00632 {
00633 for (j = 0; j < txRxMap->len; j++)
00634 {
00635 if (plan->u.simple.antennas.list[i] == txRxMap->list[j].antenna)
00636 {
00637 break;
00638 }
00639 }
00640 if (j == txRxMap->len)
00641 {
00642 return TMR_ERROR_INVALID_ANTENNA_CONFIG;
00643 }
00644 }
00645 if (NULL != plan->u.simple.tagop)
00646 {
00647 if (TMR_TAGOP_LIST == plan->u.simple.tagop->type)
00648 return TMR_ERROR_UNSUPPORTED;
00649 }
00650 }
00651
00652 return TMR_SUCCESS;
00653 }
00654
00655 TMR_Status
00656 TMR_paramSet(struct TMR_Reader *reader, TMR_Param key, const void *value)
00657 {
00658 TMR_Status ret;
00659
00660 ret = TMR_SUCCESS;
00661
00662 switch (key)
00663 {
00664 #ifdef TMR_ENABLE_BACKGROUND_READS
00665 case TMR_PARAM_READ_ASYNCOFFTIME:
00666 {
00667 if (TMR_READER_TYPE_LLRP != reader->readerType)
00668 {
00669 reader->readParams.asyncOffTime = *(uint32_t *)value;
00670 }
00671 else
00672 {
00673 goto LEVEL1;
00674 }
00675 }
00676 break;
00677 case TMR_PARAM_READ_ASYNCONTIME:
00678 reader->readParams.asyncOnTime = *(uint32_t *)value;
00679 break;
00680 LEVEL1:
00681 #endif
00682 default:
00683 ret = reader->paramSet(reader, key, value);
00684 }
00685 return ret;
00686 }
00687
00688
00689 TMR_Status
00690 TMR_paramGet(struct TMR_Reader *reader, TMR_Param key, void *value)
00691 {
00692 TMR_Status ret;
00693
00694 ret = TMR_SUCCESS;
00695
00696 switch (key)
00697 {
00698 case TMR_PARAM_READ_PLAN:
00699 {
00700 TMR_ReadPlan *plan = value;
00701 *plan = *reader->readParams.readPlan;
00702 break;
00703 }
00704 #ifdef TMR_ENABLE_BACKGROUND_READS
00705 case TMR_PARAM_READ_ASYNCOFFTIME:
00706 {
00707 if (TMR_READER_TYPE_LLRP != reader->readerType)
00708 {
00709 *(uint32_t *)value = reader->readParams.asyncOffTime;
00710 }
00711 else
00712 {
00713 goto LEVEL;
00714 }
00715 break;
00716 }
00717 case TMR_PARAM_READ_ASYNCONTIME:
00718 *(uint32_t *)value = reader->readParams.asyncOnTime;
00719 break;
00720 LEVEL:
00721 #endif
00722 default:
00723 ret = reader->paramGet(reader, key, value);
00724 }
00725 return ret;
00726 }
00727
00728
00729 TMR_Status
00730 TMR_addTransportListener(TMR_Reader *reader, TMR_TransportListenerBlock *b)
00731 {
00732
00733 b->next = reader->transportListeners;
00734 reader->transportListeners = b;
00735
00736 return TMR_SUCCESS;
00737 }
00738
00739
00740 TMR_Status
00741 TMR_removeTransportListener(TMR_Reader *reader, TMR_TransportListenerBlock *b)
00742 {
00743 TMR_TransportListenerBlock *block, **prev;
00744
00745 prev = &reader->transportListeners;
00746 block = reader->transportListeners;
00747 while (NULL != block)
00748 {
00749 if (block == b)
00750 {
00751 *prev = block->next;
00752 break;
00753 }
00754 prev = &block->next;
00755 block = block->next;
00756 }
00757 if (block == NULL)
00758 {
00759 return TMR_ERROR_INVALID;
00760 }
00761
00762 return TMR_SUCCESS;
00763 }
00764
00765
00766 void
00767 TMR__notifyTransportListeners(TMR_Reader *reader, bool tx,
00768 uint32_t dataLen, uint8_t *data,
00769 int timeout)
00770 {
00771 TMR_TransportListenerBlock *block;
00772
00773 block = reader->transportListeners;
00774 while (NULL != block)
00775 {
00776 block->listener(tx, dataLen, data, timeout, block->cookie);
00777 block = block->next;
00778 }
00779 }
00780
00781 bool
00782 TMR_memoryProvider(void *cookie, uint16_t *size, uint8_t *data)
00783 {
00784 TMR_memoryCookie *mc;
00785 int len;
00786
00787 mc = cookie;
00788
00789 if (0 == mc->firmwareSize)
00790 {
00791 return false;
00792 }
00793
00794 if (*size > mc->firmwareSize)
00795 {
00796 *size =(uint16_t) mc->firmwareSize;
00797 }
00798
00799 len = *size;
00800
00801 memcpy(data, mc->firmwareStart, len);
00802
00803 mc->firmwareSize -= len;
00804 mc->firmwareStart += len;
00805
00806 return true;
00807 }
00808
00809 #ifdef TMR_ENABLE_STDIO
00810 bool
00811 TMR_fileProvider(void *cookie, uint16_t *size, uint8_t *data)
00812 {
00813 FILE *fp;
00814 size_t len;
00815
00816 fp = cookie;
00817
00818 len = fread(data, 1, *size, fp);
00819 if (0 == len)
00820 {
00821 return false;
00822 }
00823
00824 *size = (uint16_t) len;
00825 return true;
00826 }
00827 #endif
00828
00836 TMR_Status
00837 TMR_TRD_init(TMR_TagReadData *trd)
00838 {
00839 trd->tag.protocol = TMR_TAG_PROTOCOL_NONE;
00840 trd->tag.epcByteCount = 0;
00841 trd->tag.crc = 0;
00842 trd->metadataFlags = 0;
00843 trd->phase = 0;
00844 memset(trd->gpio, 0, sizeof(trd->gpio));
00845 trd->gpioCount = 0;
00846 trd->readCount = 0;
00847 trd->rssi = 0;
00848 trd->frequency = 0;
00849 trd->dspMicros = 0;
00850 trd->timestampLow = 0;
00851 trd->timestampHigh = 0;
00852
00853 #if TMR_MAX_EMBEDDED_DATA_LENGTH
00854 trd->data.list = trd->_dataList;
00855 trd->epcMemData.list = trd->_epcMemDataList;
00856 trd->tidMemData.list = trd->_tidMemDataList;
00857 trd->userMemData.list = trd->_userMemDataList;
00858 trd->reservedMemData.list = trd->_reservedMemDataList;
00859
00860 trd->data.max = TMR_MAX_EMBEDDED_DATA_LENGTH;
00861 trd->epcMemData.max = TMR_MAX_EMBEDDED_DATA_LENGTH;
00862 trd->userMemData.max = TMR_MAX_EMBEDDED_DATA_LENGTH;
00863 trd->reservedMemData.max = TMR_MAX_EMBEDDED_DATA_LENGTH;
00864 trd->tidMemData.max = TMR_MAX_EMBEDDED_DATA_LENGTH;
00865 #else
00866 trd->data.list = NULL;
00867 trd->epcMemData.list = NULL;
00868 trd->userMemData.list = NULL;
00869 trd->tidMemData.list = NULL;
00870 trd->reservedMemData.list = NULL;
00871
00872 trd->data.max = 0;
00873 trd->epcMemData.max = 0;
00874 trd->userMemData.max = 0;
00875 trd->reservedMemData.max = 0;
00876 trd->tidMemData.max = 0;
00877 #endif
00878 trd->data.len = 0;
00879 trd->epcMemData.len = 0;
00880 trd->userMemData.len = 0;
00881 trd->tidMemData.len = 0;
00882 trd->reservedMemData.len = 0;
00883
00884 return TMR_SUCCESS;
00885 }
00886
00894 TMR_Status
00895 TMR_TRD_init_data(TMR_TagReadData *trd, uint16_t size, uint8_t *buf)
00896 {
00897 trd->data.max = size;
00898 trd->data.len = 0;
00899 trd->data.list = buf;
00900
00901 return TMR_SUCCESS;
00902 }
00903
00911 TMR_Status
00912 TMR_TRD_MEMBANK_init_data(TMR_uint8List *data, uint16_t size, uint8_t *buf)
00913 {
00914 data->max = size;
00915 data->len = 0;
00916 data->list = buf;
00917
00918 return TMR_SUCCESS;
00919 }
00920
00928 TMR_Status
00929 TMR_GEN2_init_BapParams(TMR_GEN2_Bap *bapVal, int32_t powerUpDelayUs, int32_t freqHopOfftimeUs)
00930 {
00931
00932 bapVal->powerUpDelayUs = powerUpDelayUs;
00933 bapVal->freqHopOfftimeUs=freqHopOfftimeUs;
00934
00935 return TMR_SUCCESS;
00936 }
00937
00945 TMR_Status
00946 TMR_TF_init_tag(TMR_TagFilter *filter, TMR_TagData *tag)
00947 {
00948
00949 filter->type = TMR_FILTER_TYPE_TAG_DATA;
00950 filter->u.tagData = *tag;
00951
00952 return TMR_SUCCESS;
00953 }
00954
00966 TMR_Status
00967 TMR_TF_init_gen2_select(TMR_TagFilter *filter, bool invert, TMR_GEN2_Bank bank,
00968 uint32_t bitPointer, uint16_t maskBitLength,
00969 uint8_t *mask)
00970 {
00971
00972 filter->type = TMR_FILTER_TYPE_GEN2_SELECT;
00973 filter->u.gen2Select.invert = invert;
00974 filter->u.gen2Select.bank = bank;
00975 filter->u.gen2Select.bitPointer = bitPointer;
00976 filter->u.gen2Select.maskBitLength = maskBitLength;
00977 filter->u.gen2Select.mask = mask;
00978
00979 return TMR_SUCCESS;
00980 }
00981
00982
00983 #ifdef TMR_ENABLE_ISO180006B
00984
00995 TMR_Status TMR_TF_init_ISO180006B_select(TMR_TagFilter *filter, bool invert,
00996 TMR_ISO180006B_SelectOp op,
00997 uint8_t address, uint8_t mask,
00998 uint8_t wordData[8])
00999 {
01000
01001 filter->type = TMR_FILTER_TYPE_ISO180006B_SELECT;
01002 filter->u.iso180006bSelect.invert = invert;
01003 filter->u.iso180006bSelect.op = op;
01004 filter->u.iso180006bSelect.address = address;
01005 filter->u.iso180006bSelect.mask = mask;
01006 memcpy(filter->u.iso180006bSelect.data, wordData, 8);
01007
01008 return TMR_SUCCESS;
01009 }
01010 #endif
01011
01012
01013 bool
01014 TMR_TF_match(TMR_TagFilter *filter, TMR_TagData *tag)
01015 {
01016 int32_t i, bitAddr;
01017 bool match;
01018 TMR_GEN2_Select *sel;
01019
01020 if (TMR_FILTER_TYPE_GEN2_SELECT != filter->type)
01021 {
01022 return false;
01023 }
01024
01025 if (TMR_TAG_PROTOCOL_GEN2 != tag->protocol)
01026 {
01027 return false;
01028 }
01029
01030 sel = &filter->u.gen2Select;
01031
01032 if (TMR_GEN2_BANK_EPC != sel->bank)
01033 {
01034
01035
01036
01037
01038 return false;
01039 }
01040
01041 i = 0;
01042 bitAddr = sel->bitPointer;
01043
01044
01045
01046
01047
01048 bitAddr -= 32;
01049 if (bitAddr < 0)
01050 {
01051 i -= bitAddr;
01052 bitAddr = 0;
01053 }
01054
01055 match = true;
01056 for (; i < sel->maskBitLength; i++, bitAddr++)
01057 {
01058 if (bitAddr >(int32_t) (tag->epcByteCount * 8))
01059 {
01060 match = false;
01061 break;
01062 }
01063
01064 if (((tag->epc[bitAddr / 8] >> (7 - (bitAddr & 7))) & 1) !=
01065 ((sel->mask[i / 8] >> (7 - (i & 7))) & 1))
01066 {
01067 match = false;
01068 break;
01069 }
01070 }
01071 if (sel->invert)
01072 match = match ? false : true;
01073
01074 return match;
01075 }
01076
01077
01084 TMR_Status
01085 TMR_TA_init_gen2(TMR_TagAuthentication *auth, TMR_GEN2_Password password)
01086 {
01087
01088 auth->type = TMR_AUTH_TYPE_GEN2_PASSWORD;
01089 auth->u.gen2Password = password;
01090
01091 return TMR_SUCCESS;
01092 }
01093
01100 TMR_Status
01101 TMR_TA_init_gen2_Denatran_IAV_writeCredentials(TMR_TagAuthentication *auth, uint8_t idLength, uint8_t* tagId, uint8_t len, uint8_t *data)
01102 {
01103 uint8_t i;
01104 auth->type = TMR_AUTH_TYPE_GEN2_DENATRAN_IAV_WRITE_CREDENTIALS;
01105
01106
01107 auth->u.writeCreds.credentialLength = len;
01108 if (16 != auth->u.writeCreds.credentialLength)
01109 {
01110 return TMR_ERROR_INVALID;
01111 }
01112
01113
01114 auth->u.writeCreds.tagIdLength = idLength;
01115 if (8 != auth->u.writeCreds.tagIdLength)
01116 {
01117 return TMR_ERROR_INVALID;
01118 }
01119
01120
01121 for (i = 0; i < auth->u.writeCreds.tagIdLength; i++)
01122 {
01123 memcpy(auth->u.writeCreds.tagId, tagId, auth->u.writeCreds.tagIdLength);
01124 }
01125
01126
01127 for (i = 0; i < auth->u.writeCreds.credentialLength; i++)
01128 {
01129 memcpy(auth->u.writeCreds.value, data, auth->u.writeCreds.credentialLength);
01130 }
01131
01132 return TMR_SUCCESS;
01133 }
01134
01141 TMR_Status
01142 TMR_TA_init_gen2_Denatran_IAV_writeSecCredentials(TMR_TagAuthentication *auth, uint8_t length, uint8_t* data, uint8_t len, uint8_t* credentials)
01143 {
01144 uint8_t i;
01145 auth->type = TMR_AUTH_TYPE_GEN2_DENATRAN_IAV_WRITE_SEC_CREDENTIALS;
01146
01147
01148 auth->u.writeSecCreds.credentialLength = len;
01149 if (16 != auth->u.writeSecCreds.credentialLength)
01150 {
01151 return TMR_ERROR_INVALID;
01152 }
01153
01154
01155 auth->u.writeSecCreds.dataLength = length;
01156 if (6 != auth->u.writeSecCreds.dataLength)
01157 {
01158 return TMR_ERROR_INVALID;
01159 }
01160
01161
01162 for (i = 0; i < auth->u.writeSecCreds.dataLength; i++)
01163 {
01164 memcpy(auth->u.writeSecCreds.data, data, auth->u.writeSecCreds.dataLength);
01165 }
01166
01167
01168 for (i = 0; i < auth->u.writeSecCreds.credentialLength; i++)
01169 {
01170 memcpy(auth->u.writeSecCreds.value, credentials, auth->u.writeSecCreds.credentialLength);
01171 }
01172
01173 return TMR_SUCCESS;
01174 }
01175
01180 TMR_Status
01181 TMR_STATS_init(TMR_Reader_StatsValues *stats)
01182 {
01183 if (NULL != stats)
01184 {
01185 stats->valid = TMR_READER_STATS_FLAG_NONE;
01186
01187 stats->connectedAntennas.len = 0;
01188 stats->connectedAntennas.max = TMR_SR_MAX_ANTENNA_PORTS;
01189 stats->connectedAntennas.list = stats->_connectedAntennasStorage;
01190 stats->perAntenna.len = 0;
01191 stats->perAntenna.max = TMR_SR_MAX_ANTENNA_PORTS;
01192 stats->perAntenna.list = stats->_perAntStorage;
01193 }
01194 return TMR_SUCCESS;
01195 }
01196
01203 TMR_Status
01204 TMR_GPITR_init_enable(TMR_GPITriggerRead *triggerRead, bool enable)
01205 {
01206 triggerRead->enable = enable;
01207
01208 return TMR_SUCCESS;
01209 }
01210
01227 TMR_Status
01228 TMR_RP_init_simple(TMR_ReadPlan *plan, uint8_t antennaCount,
01229 uint8_t *antennaList, TMR_TagProtocol protocol,
01230 uint32_t weight)
01231 {
01232
01233 plan->type = TMR_READ_PLAN_TYPE_SIMPLE;
01234 plan->u.simple.antennas.max = antennaCount;
01235 plan->u.simple.antennas.len = antennaCount;
01236 plan->u.simple.antennas.list = antennaList;
01237 plan->u.simple.protocol = protocol;
01238 plan->u.simple.filter = NULL;
01239 plan->u.simple.tagop = NULL;
01240 plan->weight = weight;
01241 plan->u.simple.useFastSearch = false;
01242 plan->u.simple.stopOnCount.stopNTriggerStatus = false;
01243 plan->u.simple.stopOnCount.noOfTags = 0;
01244 plan->u.simple.triggerRead.enable = false;
01245 plan->u.simple.triggerRead.gpiList.len = 0;
01246 plan->u.simple.triggerRead.gpiList.list = NULL;
01247 plan->u.simple.triggerRead.gpiList.max = 0;
01248 plan->enableAutonomousRead = false;
01249
01250 return TMR_SUCCESS;
01251 }
01252
01259 TMR_Status
01260 TMR_RP_set_stopTrigger(TMR_ReadPlan *plan, uint32_t nCount)
01261 {
01262
01263 if (TMR_READ_PLAN_TYPE_SIMPLE != plan->type)
01264 return TMR_ERROR_INVALID;
01265
01266 plan->u.simple.stopOnCount.stopNTriggerStatus = true;
01267 plan->u.simple.stopOnCount.noOfTags = nCount;
01268
01269 return TMR_SUCCESS;
01270 }
01271
01278 TMR_Status
01279 TMR_RP_set_filter(TMR_ReadPlan *plan, TMR_TagFilter *filter)
01280 {
01281
01282 if (TMR_READ_PLAN_TYPE_SIMPLE != plan->type)
01283 return TMR_ERROR_INVALID;
01284
01285 plan->u.simple.filter = filter;
01286
01287 return TMR_SUCCESS;
01288 }
01289
01296 TMR_Status
01297 TMR_RP_set_useFastSearch(TMR_ReadPlan *plan, bool useFastSearch)
01298 {
01299
01300 if (TMR_READ_PLAN_TYPE_SIMPLE != plan->type)
01301 return TMR_ERROR_INVALID;
01302
01303 plan->u.simple.useFastSearch = useFastSearch;
01304
01305 return TMR_SUCCESS;
01306 }
01307
01314 TMR_Status
01315 TMR_RP_set_enableAutonomousRead(TMR_ReadPlan *plan, bool autonomousRead)
01316 {
01317 plan->enableAutonomousRead = autonomousRead;
01318 return TMR_SUCCESS;
01319 }
01320
01327 TMR_Status
01328 TMR_RP_set_enableTriggerRead(TMR_ReadPlan *plan, TMR_GPITriggerRead *triggerRead)
01329 {
01330 if (TMR_READ_PLAN_TYPE_SIMPLE != plan->type)
01331 return TMR_ERROR_INVALID;
01332
01333 plan->u.simple.triggerRead.enable = triggerRead->enable;
01334
01335
01336
01337
01338 plan->u.simple.triggerRead.gpiList.list = NULL;
01339 plan->u.simple.triggerRead.gpiList.len = 0;
01340 plan->u.simple.triggerRead.gpiList.max = 0;
01341
01342 return TMR_SUCCESS;
01343 }
01344
01351 TMR_Status
01352 TMR_RP_set_tagop(TMR_ReadPlan *plan, TMR_TagOp *tagop)
01353 {
01354
01355 if (TMR_READ_PLAN_TYPE_SIMPLE != plan->type)
01356 return TMR_ERROR_INVALID;
01357
01358 plan->u.simple.tagop = tagop;
01359
01360 return TMR_SUCCESS;
01361 }
01362
01372 TMR_Status
01373 TMR_RP_init_multi(TMR_ReadPlan *plan, TMR_ReadPlan **plans, uint8_t planCount,
01374 uint32_t weight)
01375 {
01376 plan->type = TMR_READ_PLAN_TYPE_MULTI;
01377 plan->u.multi.plans = plans;
01378 plan->u.multi.planCount = planCount;
01379 plan->u.multi.totalWeight = 0;
01380 plan->weight = weight;
01381
01382 return TMR_SUCCESS;
01383 }
01384
01385
01394 TMR_Status
01395 TMR_TLA_init_gen2(TMR_TagLockAction *lockAction, uint16_t mask, uint16_t action)
01396 {
01397
01398 lockAction->type = TMR_LOCK_ACTION_TYPE_GEN2_LOCK_ACTION;
01399 lockAction->u.gen2LockAction.mask = mask;
01400 lockAction->u.gen2LockAction.action = action;
01401
01402 return TMR_SUCCESS;
01403 }
01404
01405
01406 #ifdef TMR_ENABLE_ISO180006B
01407
01414 TMR_Status
01415 TMR_TLA_init_ISO180006B(TMR_TagLockAction *lockAction, uint8_t address)
01416 {
01417
01418 lockAction->type = TMR_LOCK_ACTION_TYPE_ISO180006B_LOCK_ACTION;
01419 lockAction->u.iso180006bLockAction.address = address;
01420
01421 return TMR_SUCCESS;
01422 }
01423
01424 #endif
01425
01426
01434 TMR_Status
01435 TMR_TagOp_init_GEN2_WriteTag(TMR_TagOp *tagop, TMR_TagData* epc)
01436 {
01437 tagop->type = TMR_TAGOP_GEN2_WRITETAG;
01438 tagop->u.gen2.u.writeTag.epcptr = epc;
01439
01440 return TMR_SUCCESS;
01441 }
01442
01452 TMR_Status
01453 TMR_TagOp_init_GEN2_ReadData(TMR_TagOp *tagop, TMR_GEN2_Bank bank,
01454 uint32_t wordAddress, uint8_t len)
01455 {
01456
01457 tagop->type = TMR_TAGOP_GEN2_READDATA;
01458 tagop->u.gen2.u.readData.bank = bank;
01459 tagop->u.gen2.u.readData.wordAddress = wordAddress;
01460 tagop->u.gen2.u.readData.len = len;
01461
01462 return TMR_SUCCESS;
01463 }
01464
01476 TMR_Status
01477 TMR_TagOp_init_GEN2_SecureReadData(TMR_TagOp *tagop, TMR_GEN2_Bank bank, uint32_t wordAddress,
01478 uint8_t len, uint8_t tagtype, uint8_t passwordType)
01479 {
01480 tagop->type = TMR_TAGOP_GEN2_SECURE_READDATA;
01481 tagop->u.gen2.u.secureReadData.passwordType = (SecurePasswordType)passwordType;
01482 tagop->u.gen2.u.secureReadData.readData.bank = bank;
01483 tagop->u.gen2.u.secureReadData.readData.wordAddress = wordAddress;
01484 tagop->u.gen2.u.secureReadData.readData.len = len;
01485 tagop->u.gen2.u.secureReadData.type = (SecureTagType)tagtype;
01486
01487 return TMR_SUCCESS;
01488 }
01489
01501 TMR_Status
01502 TMR_TagOp_init_GEN2_SecurePassWord(TMR_TagOp *tagop, uint8_t passwordType, uint32_t gen2PassWord,
01503 uint8_t addressLength, uint8_t addressOffset, uint16_t flashOffset)
01504 {
01505
01506 tagop->u.gen2.u.secureReadData.passwordType = (SecurePasswordType)passwordType;
01507 tagop->u.gen2.u.secureReadData.password.gen2PassWord.u.gen2Password = gen2PassWord;
01508 tagop->u.gen2.u.secureReadData.password.secureAddressLength = addressLength;
01509 tagop->u.gen2.u.secureReadData.password.secureAddressOffset = addressOffset;
01510 tagop->u.gen2.u.secureReadData.password.secureFlashOffset = flashOffset;
01511
01512 return TMR_SUCCESS;
01513 }
01514
01523 TMR_Status
01524 TMR_TagOp_init_ISO180006B_ReadData(TMR_TagOp *tagop, uint8_t byteAddress, uint8_t len)
01525 {
01526
01527 tagop->type = TMR_TAGOP_ISO180006B_READDATA;
01528 tagop->u.iso180006b.u.readData.byteAddress = byteAddress;
01529 tagop->u.iso180006b.u.readData.len = len;
01530
01531 return TMR_SUCCESS;
01532 }
01533
01534
01544 TMR_Status
01545 TMR_TagOp_init_GEN2_WriteData(TMR_TagOp *tagop, TMR_GEN2_Bank bank,
01546 uint32_t wordAddress, TMR_uint16List *data)
01547 {
01548 tagop->type = TMR_TAGOP_GEN2_WRITEDATA;
01549 tagop->u.gen2.u.writeData.bank = bank;
01550 tagop->u.gen2.u.writeData.wordAddress = wordAddress;
01551 tagop->u.gen2.u.writeData.data = *data;
01552
01553 return TMR_SUCCESS;
01554 }
01555
01564 TMR_Status
01565 TMR_TagOp_init_ISO180006B_WriteData(TMR_TagOp *tagop, uint8_t byteAddress, TMR_uint8List *data)
01566 {
01567 tagop->type = TMR_TAGOP_ISO180006B_WRITEDATA;
01568 tagop->u.iso180006b.u.writeData.byteAddress = byteAddress;
01569 tagop->u.iso180006b.u.writeData.data = *data;
01570 return TMR_SUCCESS;
01571 }
01572
01580 TMR_Status
01581 TMR_TagOp_init_GEN2_Lock(TMR_TagOp *tagop, uint16_t mask, uint16_t action, TMR_GEN2_Password accessPassword)
01582 {
01583
01584 tagop->type = TMR_TAGOP_GEN2_LOCK;
01585 tagop->u.gen2.u.lock.mask = mask;
01586 tagop->u.gen2.u.lock.action = action;
01587 tagop->u.gen2.u.lock.accessPassword = accessPassword;
01588
01589 return TMR_SUCCESS;
01590 }
01591
01597 TMR_Status
01598 TMR_TagOp_init_ISO180006B_Lock(TMR_TagOp *tagop, uint8_t address)
01599 {
01600
01601 tagop->type = TMR_TAGOP_ISO180006B_LOCK;
01602 tagop->u.iso180006b.u.lock.address = address;
01603
01604 return TMR_SUCCESS;
01605 }
01606
01612 TMR_Status
01613 TMR_TagOp_init_GEN2_Kill(TMR_TagOp *tagop, TMR_GEN2_Password killPassword)
01614 {
01615
01616 tagop->type = TMR_TAGOP_GEN2_KILL;
01617 tagop->u.gen2.u.kill.password = killPassword;
01618
01619 return TMR_SUCCESS;
01620 }
01621
01622
01630 TMR_Status
01631 TMR_TagOp_init_GEN2_BlockWrite(TMR_TagOp *tagop, TMR_GEN2_Bank bank, uint32_t wordPtr, TMR_uint16List *data)
01632 {
01633 tagop->type = TMR_TAGOP_GEN2_BLOCKWRITE;
01634 tagop->u.gen2.u.blockWrite.bank = bank;
01635 tagop->u.gen2.u.blockWrite.wordPtr = wordPtr;
01636 tagop->u.gen2.u.blockWrite.data.len = data->len;
01637 tagop->u.gen2.u.blockWrite.data.list = data->list;
01638 tagop->u.gen2.u.blockWrite.data.max = data->max;
01639 return TMR_SUCCESS;
01640 }
01641
01650 TMR_Status
01651 TMR_TagOp_init_GEN2_BlockPermaLock(TMR_TagOp *tagop, uint8_t readLock, TMR_GEN2_Bank bank, uint32_t blockPtr, TMR_uint16List *mask)
01652 {
01653 tagop->type = TMR_TAGOP_GEN2_BLOCKPERMALOCK;
01654 tagop->u.gen2.u.blockPermaLock.readLock = readLock;
01655 tagop->u.gen2.u.blockPermaLock.bank = bank;
01656 tagop->u.gen2.u.blockPermaLock.blockPtr = blockPtr;
01657 tagop->u.gen2.u.blockPermaLock.mask.len = mask->len;
01658 tagop->u.gen2.u.blockPermaLock.mask.list = mask->list;
01659 tagop->u.gen2.u.blockPermaLock.mask.max = mask->max;
01660 return TMR_SUCCESS;
01661
01662 }
01663
01671 TMR_Status
01672 TMR_TagOp_init_GEN2_BlockErase(TMR_TagOp *tagop, TMR_GEN2_Bank bank, uint32_t wordPtr, uint8_t wordCount)
01673 {
01674 tagop->type = TMR_TAGOP_GEN2_BLOCKERASE;
01675 tagop->u.gen2.u.blockErase.bank = bank;
01676 tagop->u.gen2.u.blockErase.wordCount = wordCount;
01677 tagop->u.gen2.u.blockErase.wordPtr = wordPtr;
01678 return TMR_SUCCESS;
01679 }
01680
01689 #ifdef TMR_ENABLE_GEN2_CUSTOM_TAGOPS
01690
01691 TMR_Status
01692 TMR_TagOp_init_GEN2_Alien_Higgs2_PartialLoadImage(TMR_TagOp *tagop, TMR_GEN2_Password killPassword,
01693 TMR_GEN2_Password accessPassword, TMR_TagData *epc)
01694 {
01695 tagop->type = TMR_TAGOP_GEN2_ALIEN_HIGGS2_PARTIALLOADIMAGE;
01696 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_ALIEN_HIGGS_SILICON;
01697 tagop->u.gen2.u.custom.u.alien.u.higgs2.u.partialLoadImage.accessPassword = accessPassword;
01698 tagop->u.gen2.u.custom.u.alien.u.higgs2.u.partialLoadImage.killPassword = killPassword;
01699 tagop->u.gen2.u.custom.u.alien.u.higgs2.u.partialLoadImage.epcptr = epc;
01700
01701 return TMR_SUCCESS;
01702 }
01703
01713 TMR_Status
01714 TMR_TagOp_init_GEN2_Alien_Higgs2_FullLoadImage(TMR_TagOp *tagop, TMR_GEN2_Password killPassword,
01715 TMR_GEN2_Password accessPassword, uint16_t lockBits,
01716 uint16_t pcWord, TMR_TagData *epc)
01717 {
01718 tagop->type = TMR_TAGOP_GEN2_ALIEN_HIGGS2_FULLLOADIMAGE;
01719 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_ALIEN_HIGGS_SILICON;
01720 tagop->u.gen2.u.custom.u.alien.u.higgs2.u.fullLoadImage.accessPassword = accessPassword;
01721 tagop->u.gen2.u.custom.u.alien.u.higgs2.u.fullLoadImage.killPassword = killPassword;
01722 tagop->u.gen2.u.custom.u.alien.u.higgs2.u.fullLoadImage.lockBits = lockBits;
01723 tagop->u.gen2.u.custom.u.alien.u.higgs2.u.fullLoadImage.pcWord = pcWord;
01724 tagop->u.gen2.u.custom.u.alien.u.higgs2.u.fullLoadImage.epcptr = epc;
01725
01726 return TMR_SUCCESS;
01727 }
01728
01738 TMR_Status TMR_TagOp_init_GEN2_Alien_Higgs3_FastLoadImage(TMR_TagOp *tagop, TMR_GEN2_Password currentAccessPassword,
01739 TMR_GEN2_Password accessPassword, TMR_GEN2_Password killPassword,
01740 uint16_t pcWord, TMR_TagData *epc)
01741 {
01742 tagop->type = TMR_TAGOP_GEN2_ALIEN_HIGGS3_FASTLOADIMAGE;
01743 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_ALIEN_HIGGS3_SILICON;
01744 tagop->u.gen2.u.custom.u.alien.u.higgs3.u.fastLoadImage.currentAccessPassword = currentAccessPassword;
01745 tagop->u.gen2.u.custom.u.alien.u.higgs3.u.fastLoadImage.killPassword = killPassword;
01746 tagop->u.gen2.u.custom.u.alien.u.higgs3.u.fastLoadImage.accessPassword = accessPassword;
01747 tagop->u.gen2.u.custom.u.alien.u.higgs3.u.fastLoadImage.pcWord = pcWord;
01748 tagop->u.gen2.u.custom.u.alien.u.higgs3.u.fastLoadImage.epcptr = epc;
01749
01750 return TMR_SUCCESS;
01751 }
01752
01762 TMR_Status TMR_TagOp_init_GEN2_Alien_Higgs3_LoadImage(TMR_TagOp *tagop, TMR_GEN2_Password currentAccessPassword,
01763 TMR_GEN2_Password accessPassword, TMR_GEN2_Password killPassword,
01764 uint16_t pcWord, TMR_uint8List *epcAndUserData)
01765 {
01766 tagop->type = TMR_TAGOP_GEN2_ALIEN_HIGGS3_LOADIMAGE;
01767 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_ALIEN_HIGGS3_SILICON;
01768 tagop->u.gen2.u.custom.u.alien.u.higgs3.u.loadImage.currentAccessPassword = currentAccessPassword;
01769 tagop->u.gen2.u.custom.u.alien.u.higgs3.u.loadImage.killPassword = killPassword;
01770 tagop->u.gen2.u.custom.u.alien.u.higgs3.u.loadImage.accessPassword = accessPassword;
01771 tagop->u.gen2.u.custom.u.alien.u.higgs3.u.loadImage.pcWord = pcWord;
01772 tagop->u.gen2.u.custom.u.alien.u.higgs3.u.loadImage.epcAndUserData = epcAndUserData;
01773
01774 return TMR_SUCCESS;
01775 }
01776
01783 TMR_Status TMR_TagOp_init_GEN2_Alien_Higgs3_BlockReadLock(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword, uint8_t lockBits)
01784 {
01785 tagop->type = TMR_TAGOP_GEN2_ALIEN_HIGGS3_BLOCKREADLOCK;
01786 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_ALIEN_HIGGS3_SILICON;
01787 tagop->u.gen2.u.custom.u.alien.u.higgs3.u.blockReadLock.accessPassword = accessPassword;
01788 tagop->u.gen2.u.custom.u.alien.u.higgs3.u.blockReadLock.lockBits = lockBits;
01789
01790 return TMR_SUCCESS;
01791 }
01792
01798 TMR_Status TMR_TagOp_init_GEN2_NXP_G2I_SetReadProtect(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword)
01799 {
01800 tagop->type = TMR_TAGOP_GEN2_NXP_SETREADPROTECT;
01801 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_G2I_SILICON;
01802 tagop->u.gen2.u.custom.u.nxp.u.setReadProtect.accessPassword = accessPassword;
01803 return TMR_SUCCESS;
01804 }
01805
01811 TMR_Status TMR_TagOp_init_GEN2_NXP_G2X_SetReadProtect(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword)
01812 {
01813 tagop->type = TMR_TAGOP_GEN2_NXP_SETREADPROTECT;
01814 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_G2X_SILICON;
01815 tagop->u.gen2.u.custom.u.nxp.u.setReadProtect.accessPassword = accessPassword;
01816 return TMR_SUCCESS;
01817 }
01818
01824 TMR_Status TMR_TagOp_init_GEN2_NXP_G2I_ResetReadProtect(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword)
01825 {
01826 tagop->type = TMR_TAGOP_GEN2_NXP_RESETREADPROTECT;
01827 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_G2I_SILICON;
01828 tagop->u.gen2.u.custom.u.nxp.u.resetReadProtect.accessPassword = accessPassword;
01829 return TMR_SUCCESS;
01830 }
01831
01837 TMR_Status TMR_TagOp_init_GEN2_NXP_G2X_ResetReadProtect(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword)
01838 {
01839 tagop->type = TMR_TAGOP_GEN2_NXP_RESETREADPROTECT;
01840 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_G2X_SILICON;
01841 tagop->u.gen2.u.custom.u.nxp.u.resetReadProtect.accessPassword = accessPassword;
01842 return TMR_SUCCESS;
01843 }
01844
01852 TMR_Status TMR_TagOp_init_GEN2_NXP_G2I_ChangeEAS(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword, bool resetEAS)
01853 {
01854 tagop->type = TMR_TAGOP_GEN2_NXP_CHANGEEAS;
01855 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_G2I_SILICON;
01856 tagop->u.gen2.u.custom.u.nxp.u.changeEAS.accessPassword = accessPassword;
01857 tagop->u.gen2.u.custom.u.nxp.u.changeEAS.reset = resetEAS;
01858
01859 return TMR_SUCCESS;
01860 }
01861
01869 TMR_Status TMR_TagOp_init_GEN2_NXP_G2X_ChangeEAS(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword, bool resetEAS)
01870 {
01871 tagop->type = TMR_TAGOP_GEN2_NXP_CHANGEEAS;
01872 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_G2X_SILICON;
01873 tagop->u.gen2.u.custom.u.nxp.u.changeEAS.accessPassword = accessPassword;
01874 tagop->u.gen2.u.custom.u.nxp.u.changeEAS.reset = resetEAS;
01875
01876 return TMR_SUCCESS;
01877 }
01878
01886 TMR_Status TMR_TagOp_init_GEN2_NXP_G2I_EASAlarm(TMR_TagOp *tagop, TMR_GEN2_DivideRatio dr, TMR_GEN2_TagEncoding m, TMR_GEN2_TrExt trExt)
01887 {
01888 tagop->type = TMR_TAGOP_GEN2_NXP_EASALARM;
01889 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_G2I_SILICON;
01890 tagop->u.gen2.u.custom.u.nxp.u.EASAlarm.dr = dr;
01891 tagop->u.gen2.u.custom.u.nxp.u.EASAlarm.m = m;
01892 tagop->u.gen2.u.custom.u.nxp.u.EASAlarm.trExt = trExt;
01893 return TMR_SUCCESS;
01894 }
01895
01896 TMR_Status TMR_TagOp_init_GEN2_NXP_AES_Untraceable(TMR_TagOp *tagop,TMR_GEN2_UNTRACEABLE_Epc epc, int epclen , TMR_GEN2_UNTRACEABLE_Tid tid, TMR_GEN2_UNTRACEABLE_UserMemory user,
01897 TMR_GEN2_UNTRACEABLE_Range range, TMR_TagOp_GEN2_NXP_Untraceable *untraceable)
01898 {
01899 tagop->type = TMR_TAGOP_GEN2_NXP_UNTRACEABLE;
01900 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_AES_UCODE;
01901 tagop->u.gen2.u.custom.u.nxp.u.untraceable.epc = epc;
01902 tagop->u.gen2.u.custom.u.nxp.u.untraceable.epcLength = epclen;
01903 tagop->u.gen2.u.custom.u.nxp.u.untraceable.tid = tid;
01904 tagop->u.gen2.u.custom.u.nxp.u.untraceable.userMemory = user;
01905 tagop->u.gen2.u.custom.u.nxp.u.untraceable.range = range;
01906 if(untraceable->auth.authType == UNTRACEABLE_WITH_AUTHENTICATION)
01907 {
01908 tagop->u.gen2.u.custom.u.nxp.u.untraceable.subCommand = 0x02;
01909 tagop->u.gen2.u.custom.u.nxp.u.untraceable.auth.tam1Auth = untraceable->auth.tam1Auth;
01910 tagop->u.gen2.u.custom.u.nxp.u.untraceable.auth.tam1Auth.Authentication |= 0x03;
01911 }
01912 else
01913 {
01914 tagop->u.gen2.u.custom.u.nxp.u.untraceable.subCommand = 0x03;
01915 tagop->u.gen2.u.custom.u.nxp.u.untraceable.auth.accessPassword = untraceable->auth.accessPassword;
01916 }
01917 return TMR_SUCCESS;
01918 }
01919
01920 TMR_Status TMR_TagOp_init_GEN2_NXP_AES_Authenticate(TMR_TagOp *tagop, TMR_TagOp_GEN2_NXP_Authenticate *authenticate)
01921 {
01922 tagop->type = TMR_TAGOP_GEN2_NXP_AUTHENTICATE;
01923 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_AES_UCODE;
01924 if(authenticate->type == TAM1_AUTHENTICATION)
01925 {
01926 tagop->u.gen2.u.custom.u.nxp.u.authenticate.type = authenticate->type;
01927 tagop->u.gen2.u.custom.u.nxp.u.authenticate.subCommand = 0x01;
01928 tagop->u.gen2.u.custom.u.nxp.u.authenticate.tam1Auth = authenticate->tam1Auth;
01929 tagop->u.gen2.u.custom.u.nxp.u.authenticate.tam1Auth.Authentication |= 0x03;
01930 }
01931 else
01932 {
01933 tagop->u.gen2.u.custom.u.nxp.u.authenticate.tam1Auth = authenticate->tam2Auth.tam1Auth;
01934 tagop->u.gen2.u.custom.u.nxp.u.authenticate.type = authenticate->type;
01935 tagop->u.gen2.u.custom.u.nxp.u.authenticate.subCommand = 0x01;
01936 tagop->u.gen2.u.custom.u.nxp.u.authenticate.tam2Auth = authenticate->tam2Auth;
01937 tagop->u.gen2.u.custom.u.nxp.u.authenticate.tam1Auth.Authentication |= 0x07;
01938 }
01939 return TMR_SUCCESS;
01940 }
01941
01942 TMR_Status TMR_TagOp_init_GEN2_NXP_AES_Tam2authentication(TMR_TagOp_GEN2_NXP_Tam2Authentication *auth, TMR_NXP_KeyId keyid, TMR_uint8List *key,
01943 TMR_uint8List *ichallenge, TMR_NXP_Profile profile, uint16_t Offset,uint8_t blockCount,bool sendRawData)
01944 {
01945 auth->tam1Auth.Authentication = sendRawData ? 0x80 : 0x00;
01946 auth->tam1Auth.CSI = 0x00;
01947 auth->tam1Auth.KeyLength = 0x10;
01948 auth->tam1Auth.IchallengeLength = 0x0A;
01949 auth->tam1Auth.Ichallenge.len = ichallenge->len;
01950 auth->tam1Auth.Ichallenge.list = ichallenge->list;
01951 auth->tam1Auth.Ichallenge.max = ichallenge->max;
01952 auth->tam1Auth.Key.len = key->len;
01953 auth->tam1Auth.Key.list = key->list;
01954 auth->tam1Auth.Key.max = key->max;
01955 auth->tam1Auth.keyID = keyid;
01956 auth->Offset = Offset;
01957 auth->BlockCount = blockCount;
01958 auth->ProtMode = 0x0001;
01959 auth->profile = profile;
01960 return TMR_SUCCESS;
01961 }
01962 TMR_Status TMR_TagOp_init_GEN2_NXP_AES_ReadBuffer(TMR_TagOp *tagop, uint16_t wordPointer, uint16_t bitCount, TMR_TagOp_GEN2_NXP_Readbuffer *readbuffer)
01963 {
01964 tagop->type = TMR_TAGOP_GEN2_NXP_READBUFFER;
01965 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_AES_UCODE;
01966 tagop->u.gen2.u.custom.u.nxp.u.readBuffer.wordPointer = wordPointer;
01967 tagop->u.gen2.u.custom.u.nxp.u.readBuffer.bitCount = bitCount;
01968 if(readbuffer->authenticate.type == TAM1_AUTHENTICATION)
01969 {
01970 tagop->u.gen2.u.custom.u.nxp.u.readBuffer.authenticate.type = readbuffer->authenticate.type;
01971 tagop->u.gen2.u.custom.u.nxp.u.readBuffer.authenticate.subCommand = 0x04;
01972 tagop->u.gen2.u.custom.u.nxp.u.readBuffer.authenticate.tam1Auth = readbuffer->authenticate.tam1Auth;
01973 tagop->u.gen2.u.custom.u.nxp.u.readBuffer.authenticate.tam1Auth.Authentication |= 0x00;
01974 }
01975 else
01976 {
01977 tagop->u.gen2.u.custom.u.nxp.u.readBuffer.authenticate.tam1Auth = readbuffer->authenticate.tam2Auth.tam1Auth;
01978 tagop->u.gen2.u.custom.u.nxp.u.readBuffer.authenticate.type = readbuffer->authenticate.type;
01979 tagop->u.gen2.u.custom.u.nxp.u.readBuffer.authenticate.subCommand = 0x04;
01980 tagop->u.gen2.u.custom.u.nxp.u.readBuffer.authenticate.tam2Auth = readbuffer->authenticate.tam2Auth;
01981 tagop->u.gen2.u.custom.u.nxp.u.readBuffer.authenticate.tam1Auth.Authentication |= 0x04;
01982 }
01983 return TMR_SUCCESS;
01984 }
01985
01986 TMR_Status TMR_TagOp_init_GEN2_NXP_AES_Tam1authentication(TMR_TagOp_GEN2_NXP_Tam1Authentication *auth, TMR_NXP_KeyId keyid, TMR_uint8List *key,
01987 TMR_uint8List *ichallenge ,bool sendRawData )
01988 {
01989 auth->Authentication = sendRawData ? 0x80 : 0x00;
01990 auth->CSI = 0x00;
01991 auth->KeyLength = 0x10;
01992 auth->IchallengeLength = 0x0A;
01993 auth->Ichallenge.len = ichallenge->len;
01994 auth->Ichallenge.list = ichallenge->list;
01995 auth->Ichallenge.max = ichallenge->max;
01996 auth->Key.len = key->len;
01997 auth->Key.list = key->list;
01998 auth->Key.max = key->max;
01999 auth->keyID = keyid;
02000 return TMR_SUCCESS;
02001 }
02002
02010 TMR_Status TMR_TagOp_init_GEN2_NXP_G2X_EASAlarm(TMR_TagOp *tagop, TMR_GEN2_DivideRatio dr, TMR_GEN2_TagEncoding m, TMR_GEN2_TrExt trExt)
02011 {
02012 tagop->type = TMR_TAGOP_GEN2_NXP_EASALARM;
02013 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_G2X_SILICON;
02014 tagop->u.gen2.u.custom.u.nxp.u.EASAlarm.dr = dr;
02015 tagop->u.gen2.u.custom.u.nxp.u.EASAlarm.m = m;
02016 tagop->u.gen2.u.custom.u.nxp.u.EASAlarm.trExt = trExt;
02017
02018 return TMR_SUCCESS;
02019 }
02020
02027 TMR_Status TMR_TagOp_init_GEN2_NXP_G2I_Calibrate(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword)
02028 {
02029 tagop->type = TMR_TAGOP_GEN2_NXP_CALIBRATE;
02030 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_G2I_SILICON;
02031 tagop->u.gen2.u.custom.u.nxp.u.calibrate.accessPassword = accessPassword;
02032
02033 return TMR_SUCCESS;
02034 }
02035
02042 TMR_Status TMR_TagOp_init_GEN2_NXP_G2X_Calibrate(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword)
02043 {
02044 tagop->type = TMR_TAGOP_GEN2_NXP_CALIBRATE;
02045 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_G2X_SILICON;
02046 tagop->u.gen2.u.custom.u.nxp.u.calibrate.accessPassword = accessPassword;
02047
02048 return TMR_SUCCESS;
02049 }
02050
02057 TMR_Status TMR_TagOp_init_GEN2_NXP_G2I_ChangeConfig(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword, TMR_NXP_ConfigWord configWord)
02058 {
02059 tagop->type = TMR_TAGOP_GEN2_NXP_CHANGECONFIG;
02060 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_G2I_SILICON;
02061 tagop->u.gen2.u.custom.u.nxp.u.changeConfig.accessPassword = accessPassword;
02062 tagop->u.gen2.u.custom.u.nxp.u.changeConfig.configWord = configWord;
02063
02064 return TMR_SUCCESS;
02065 }
02066
02073 TMR_Status TMR_TagOp_init_GEN2_NXP_G2X_ChangeConfig(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword, TMR_NXP_ConfigWord configWord)
02074 {
02075 tagop->type = TMR_TAGOP_GEN2_NXP_CHANGECONFIG;
02076 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_NXP_G2X_SILICON;
02077 tagop->u.gen2.u.custom.u.nxp.u.changeConfig.accessPassword = accessPassword;
02078 tagop->u.gen2.u.custom.u.nxp.u.changeConfig.configWord = configWord;
02079
02080 return TMR_SUCCESS;
02081 }
02082
02090 TMR_Status
02091 TMR_TagOp_init_GEN2_Impinj_Monza4_QTReadWrite(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword,
02092 TMR_Monza4_ControlByte controlByte, TMR_Monza4_Payload payload)
02093 {
02094 tagop->type = TMR_TAGOP_GEN2_IMPINJ_MONZA4_QTREADWRITE;
02095 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IMPINJ_MONZA4_SILICON;
02096 tagop->u.gen2.u.custom.u.impinj.u.monza4.u.qtReadWrite.accessPassword = accessPassword;
02097 tagop->u.gen2.u.custom.u.impinj.u.monza4.u.qtReadWrite.controlByte = controlByte;
02098 tagop->u.gen2.u.custom.u.impinj.u.monza4.u.qtReadWrite.payload = payload;
02099
02100 return TMR_SUCCESS;
02101 }
02102
02108 TMR_Status
02109 TMR_TagOp_init_GEN2_Denatran_IAV_Activate_Secure_Mode(TMR_TagOp *tagop, uint8_t payload)
02110 {
02111 tagop->type = TMR_TAGOP_GEN2_DENATRAN_IAV_ACTIVATESECUREMODE;
02112 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_DENATRAN_IAV_SILICON;
02113 tagop->u.gen2.u.custom.u.IavDenatran.u.secureMode.mode = GEN2_ACTIVATE_SECURE_MODE;
02114 tagop->u.gen2.u.custom.u.IavDenatran.u.secureMode.payload = payload;
02115
02116 return TMR_SUCCESS;
02117 }
02118
02124 TMR_Status
02125 TMR_TagOp_init_GEN2_Denatran_IAV_Authenticate_OBU(TMR_TagOp *tagop, uint8_t payload)
02126 {
02127 tagop->type = TMR_TAGOP_GEN2_DENATRAN_IAV_AUTHENTICATEOBU;
02128 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_DENATRAN_IAV_SILICON;
02129 tagop->u.gen2.u.custom.u.IavDenatran.u.authenticateOBU.mode = GEN2_AUTHENTICATE_OBU;
02130 tagop->u.gen2.u.custom.u.IavDenatran.u.authenticateOBU.payload = payload;
02131
02132 return TMR_SUCCESS;
02133 }
02134
02141 TMR_Status
02142 TMR_TagOp_init_GEN2_Denatran_IAV_Activate_Siniav_Mode(TMR_TagOp *tagop, uint8_t payload, TMR_uint8List *token)
02143 {
02144 uint8_t tokenDesc;
02145
02146 tagop->type = TMR_TAGOP_GEN2_ACTIVATE_SINIAV_MODE;
02147 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_DENATRAN_IAV_SILICON;
02148 tagop->u.gen2.u.custom.u.IavDenatran.u.activateSiniavMode.mode = GEN2_ACTIVATE_SINIAV_MODE;
02149 tagop->u.gen2.u.custom.u.IavDenatran.u.activateSiniavMode.payload = payload;
02150
02157 tokenDesc = 0x03 & payload;
02158 if (0x01 == tokenDesc)
02159 {
02160
02161 if (0x08 != token->len)
02162 {
02163 return TMR_ERROR_INVALID;
02164 }
02165 memcpy(tagop->u.gen2.u.custom.u.IavDenatran.u.activateSiniavMode.token, token->list, token->len);
02166 tagop->u.gen2.u.custom.u.IavDenatran.u.activateSiniavMode.isTokenDesc = true;
02167 }
02168 else
02169 {
02170 tagop->u.gen2.u.custom.u.IavDenatran.u.activateSiniavMode.isTokenDesc = false;
02171 }
02172
02173 return TMR_SUCCESS;
02174 }
02175
02181 TMR_Status
02182 TMR_TagOp_init_GEN2_Denatran_IAV_OBU_Auth_ID(TMR_TagOp *tagop, uint8_t payload)
02183 {
02184 tagop->type = TMR_TAGOP_GEN2_OBU_AUTH_ID;
02185 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_DENATRAN_IAV_SILICON;
02186 tagop->u.gen2.u.custom.u.IavDenatran.u.obuAuthId.mode = GEN2_OBU_AUTH_ID;
02187 tagop->u.gen2.u.custom.u.IavDenatran.u.obuAuthId.payload = payload;
02188
02189 return TMR_SUCCESS;
02190 }
02191
02197 TMR_Status
02198 TMR_TagOp_init_GEN2_Denatran_IAV_OBU_Auth_Full_Pass1(TMR_TagOp *tagop, uint8_t payload)
02199 {
02200 tagop->type = TMR_TAGOP_GEN2_AUTHENTICATE_OBU_FULL_PASS1;
02201 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_DENATRAN_IAV_SILICON;
02202 tagop->u.gen2.u.custom.u.IavDenatran.u.obuAuthFullPass1.mode = GEN2_AUTHENTICATE_OBU_FULL_PASS1;
02203 tagop->u.gen2.u.custom.u.IavDenatran.u.obuAuthFullPass1.payload = payload;
02204
02205 return TMR_SUCCESS;
02206 }
02207
02213 TMR_Status
02214 TMR_TagOp_init_GEN2_Denatran_IAV_OBU_Auth_Full_Pass2(TMR_TagOp *tagop, uint8_t payload)
02215 {
02216 tagop->type = TMR_TAGOP_GEN2_AUTHENTICATE_OBU_FULL_PASS2;
02217 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_DENATRAN_IAV_SILICON;
02218 tagop->u.gen2.u.custom.u.IavDenatran.u.obuAuthFullPass2.mode = GEN2_AUTHENTICATE_OBU_FULL_PASS2;
02219 tagop->u.gen2.u.custom.u.IavDenatran.u.obuAuthFullPass2.payload = payload;
02220
02221 return TMR_SUCCESS;
02222 }
02223
02230 TMR_Status
02231 TMR_TagOp_init_GEN2_Denatran_IAV_OBU_ReadFromMemMap(TMR_TagOp *tagop, uint8_t payload, uint16_t wordAddress)
02232 {
02233 tagop->type = TMR_TAGOP_GEN2_OBU_READ_FROM_MEM_MAP;
02234 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_DENATRAN_IAV_SILICON;
02235 tagop->u.gen2.u.custom.u.IavDenatran.u.obuReadFromMemMap.mode = GEN2_OBU_READ_FROM_MEM_MAP;
02236 tagop->u.gen2.u.custom.u.IavDenatran.u.obuReadFromMemMap.payload = payload;
02237 tagop->u.gen2.u.custom.u.IavDenatran.u.obuReadFromMemMap.readPtr = wordAddress;
02238
02239 return TMR_SUCCESS;
02240 }
02241
02250 TMR_Status
02251 TMR_TagOp_init_GEN2_Denatran_IAV_OBU_WriteToMemMap(TMR_TagOp *tagop, uint8_t payload, uint16_t wordAddress, uint16_t word, uint8_t* tagId, uint8_t* data)
02252 {
02253 tagop->type = TMR_TAGOP_GEN2_OBU_WRITE_TO_MEM_MAP;
02254 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_DENATRAN_IAV_SILICON;
02255 tagop->u.gen2.u.custom.u.IavDenatran.u.obuWriteToMemMap.mode = GEN2_OBU_WRITE_TO_MEM_MAP;
02256 tagop->u.gen2.u.custom.u.IavDenatran.u.obuWriteToMemMap.payload = payload;
02257 tagop->u.gen2.u.custom.u.IavDenatran.u.obuWriteToMemMap.writePtr = wordAddress;
02258 tagop->u.gen2.u.custom.u.IavDenatran.u.obuWriteToMemMap.wordData = word;
02259 tagop->u.gen2.u.custom.u.IavDenatran.u.obuWriteToMemMap.tagIdentification = tagId;
02260 tagop->u.gen2.u.custom.u.IavDenatran.u.obuWriteToMemMap.dataBuf = data;
02261
02262 return TMR_SUCCESS;
02263 }
02264
02273 TMR_Status
02274 TMR_TagOp_init_GEN2_Denatran_IAV_WriteSec(TMR_TagOp *tagop, uint8_t payload, uint8_t* data, uint8_t* credentials)
02275 {
02276 tagop->type = TMR_TAGOP_GEN2_DENATRAN_IAV_WRITE_SEC;
02277 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_DENATRAN_IAV_SILICON;
02278 tagop->u.gen2.u.custom.u.IavDenatran.u.writeSec.mode = GEN2_WRITE_SEC;
02279 tagop->u.gen2.u.custom.u.IavDenatran.u.writeSec.payload = payload;
02280 tagop->u.gen2.u.custom.u.IavDenatran.u.writeSec.dataWords = data;
02281 tagop->u.gen2.u.custom.u.IavDenatran.u.writeSec.dataBuf = credentials;
02282
02283 return TMR_SUCCESS;
02284 }
02285
02291 TMR_Status
02292 TMR_TagOp_init_GEN2_Denatran_IAV_OBU_Auth_Full_Pass(TMR_TagOp *tagop, uint8_t payload)
02293 {
02294 tagop->type = TMR_TAGOP_GEN2_DENATRAN_IAV_AUTHENTICATE_OBU_FULL_PASS;
02295 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_DENATRAN_IAV_SILICON;
02296 tagop->u.gen2.u.custom.u.IavDenatran.u.obuAuthFullPass.mode = GEN2_AUTHENTICATE_OBU_FULL_PASS;
02297 tagop->u.gen2.u.custom.u.IavDenatran.u.obuAuthFullPass.payload = payload;
02298
02299 return TMR_SUCCESS;
02300 }
02301
02307 TMR_Status
02308 TMR_TagOp_init_GEN2_Denatran_IAV_G0_PA_OBU_Auth(TMR_TagOp *tagop, uint8_t payload)
02309 {
02310 tagop->type = TMR_TAGOP_GEN2_DENATRAN_IAV_G0_PA_OBU_AUTHENTICATE_ID;
02311 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_DENATRAN_IAV_SILICON;
02312 tagop->u.gen2.u.custom.u.IavDenatran.u.g0paobuauthid.mode = GEN2_PA_G0_AUTHENTICATE;
02313 tagop->u.gen2.u.custom.u.IavDenatran.u.g0paobuauthid.payload = payload;
02314
02315 return TMR_SUCCESS;
02316 }
02317
02322 TMR_Status
02323 TMR_TagOp_init_GEN2_Denatran_IAV_GetTokenId(TMR_TagOp *tagop)
02324 {
02325 tagop->type = TMR_TAGOP_GEN2_DENATRAN_IAV_GET_TOKEN_ID;
02326 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_DENATRAN_IAV_SILICON;
02327 tagop->u.gen2.u.custom.u.IavDenatran.u.getTokenId.mode = GEN2_GET_TOKEN_ID;
02328
02329 return TMR_SUCCESS;
02330 }
02331
02338 TMR_Status
02339 TMR_TagOp_init_GEN2_Denatran_IAV_ReadSec(TMR_TagOp *tagop, uint8_t payload, uint16_t wordAddress)
02340 {
02341 tagop->type = TMR_TAGOP_GEN2_DENATRAN_IAV_READ_SEC;
02342 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_DENATRAN_IAV_SILICON;
02343 tagop->u.gen2.u.custom.u.IavDenatran.u.readSec.mode = GEN2_READ_SEC;
02344 tagop->u.gen2.u.custom.u.IavDenatran.u.readSec.payload = payload;
02345 tagop->u.gen2.u.custom.u.IavDenatran.u.readSec.readPtr = wordAddress;
02346
02347 return TMR_SUCCESS;
02348 }
02349
02357 TMR_Status
02358 TMR_TagOp_init_GEN2_IDS_SL900A_GetCalibrationData(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword,
02359 PasswordLevel level, uint32_t password)
02360 {
02361 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_GETCALIBRATIONDATA;
02362 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02363 tagop->u.gen2.u.custom.u.ids.u.calibrationData.AccessPassword = accessPassword;
02364 tagop->u.gen2.u.custom.u.ids.u.calibrationData.CommandCode = 0xA9;
02365 tagop->u.gen2.u.custom.u.ids.u.calibrationData.Password = password;
02366 tagop->u.gen2.u.custom.u.ids.u.calibrationData.sl900A.level = level;
02367
02368 return TMR_SUCCESS;
02369 }
02370
02380 TMR_Status
02381 TMR_TagOp_init_GEN2_IDS_SL900A_SetPassword(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword, PasswordLevel level,
02382 uint32_t password, PasswordLevel newPasswordLevel, uint32_t newPassword)
02383 {
02384 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_SETPASSWORD;
02385 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02386 tagop->u.gen2.u.custom.u.ids.u.setPassword.AccessPassword = accessPassword;
02387 tagop->u.gen2.u.custom.u.ids.u.setPassword.CommandCode = 0xA0;
02388 tagop->u.gen2.u.custom.u.ids.u.setPassword.sl900A.level = level;
02389 tagop->u.gen2.u.custom.u.ids.u.setPassword.Password = password;
02390 tagop->u.gen2.u.custom.u.ids.u.setPassword.NewPasswordLevel = newPasswordLevel;
02391 tagop->u.gen2.u.custom.u.ids.u.setPassword.NewPassword = newPassword;
02392
02393 return TMR_SUCCESS;
02394 }
02403 TMR_Status
02404 TMR_TagOp_init_GEN2_IDS_SL900A_SetCalibrationData(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword, PasswordLevel level,
02405 uint32_t password, TMR_TagOp_GEN2_IDS_SL900A_CalibrationData *data)
02406 {
02407 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_SETCALIBRATIONDATA;
02408 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02409 tagop->u.gen2.u.custom.u.ids.u.setCalibration.AccessPassword = accessPassword;
02410 tagop->u.gen2.u.custom.u.ids.u.setCalibration.CommandCode = 0xA5;
02411 tagop->u.gen2.u.custom.u.ids.u.setCalibration.Password = password;
02412 tagop->u.gen2.u.custom.u.ids.u.setCalibration.sl900A.level = level;
02413 tagop->u.gen2.u.custom.u.ids.u.setCalibration.cal.raw = data->raw;
02414
02415 return TMR_SUCCESS;
02416 }
02417
02426 TMR_Status
02427 TMR_TagOp_init_GEN2_IDS_SL900A_SetSfeParameters(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword, PasswordLevel level,
02428 uint32_t password, TMR_TagOp_GEN2_IDS_SL900A_SfeParameters *data)
02429 {
02430 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_SETSFEPARAMETERS;
02431 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02432 tagop->u.gen2.u.custom.u.ids.u.setSfeParameters.AccessPassword = accessPassword;
02433 tagop->u.gen2.u.custom.u.ids.u.setSfeParameters.CommandCode = 0xA4;
02434 tagop->u.gen2.u.custom.u.ids.u.setSfeParameters.Password = password;
02435 tagop->u.gen2.u.custom.u.ids.u.setSfeParameters.sl900A.level = level;
02436 tagop->u.gen2.u.custom.u.ids.u.setSfeParameters.sfe = data;
02437
02438 return TMR_SUCCESS;
02439 }
02440
02449 TMR_Status
02450 TMR_TagOp_init_GEN2_IDS_SL900A_GetSensorValue(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword,
02451 PasswordLevel level, uint32_t password, Sensor type)
02452 {
02453 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_GETSENSOR;
02454 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02455 tagop->u.gen2.u.custom.u.ids.u.sensor.AccessPassword = accessPassword;
02456 tagop->u.gen2.u.custom.u.ids.u.sensor.CommandCode = 0xAD;
02457 tagop->u.gen2.u.custom.u.ids.u.sensor.Password = password;
02458 tagop->u.gen2.u.custom.u.ids.u.sensor.sl900A.level = level;
02459 tagop->u.gen2.u.custom.u.ids.u.sensor.sl900A.sensortype = type;
02460
02461 return TMR_SUCCESS;
02462 }
02463
02471 TMR_Status
02472 TMR_TagOp_init_GEN2_IDS_SL900A_GetMeasurementSetup(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword,
02473 PasswordLevel level, uint32_t password)
02474 {
02475 tagop->type =TMR_TAGOP_GEN2_IDS_SL900A_GETMEASUREMENTSETUP;
02476 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02477 tagop->u.gen2.u.custom.u.ids.u.measurementSetup.AccessPassword = accessPassword;
02478 tagop->u.gen2.u.custom.u.ids.u.measurementSetup.CommandCode = 0xA3;
02479 tagop->u.gen2.u.custom.u.ids.u.measurementSetup.Password = password;
02480 tagop->u.gen2.u.custom.u.ids.u.measurementSetup.sl900A.level = level;
02481
02482 return TMR_SUCCESS;
02483 }
02484
02492 TMR_Status
02493 TMR_TagOp_init_GEN2_IDS_SL900A_GetLogState(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword,
02494 PasswordLevel level, uint32_t password)
02495 {
02496 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_GETLOGSTATE;
02497 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02498 tagop->u.gen2.u.custom.u.ids.u.getLog.AccessPassword = accessPassword;
02499 tagop->u.gen2.u.custom.u.ids.u.getLog.CommandCode = 0xA8;
02500 tagop->u.gen2.u.custom.u.ids.u.getLog.Password = password;
02501 tagop->u.gen2.u.custom.u.ids.u.getLog.sl900A.level = level;
02502
02503 return TMR_SUCCESS;
02504 }
02505
02520 TMR_Status
02521 TMR_TagOp_init_GEN2_IDS_SL900A_SetLogMode(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword, PasswordLevel level,
02522 uint32_t password, LoggingForm form, StorageRule rule, bool Ext1Enable,
02523 bool Ext2Enable, bool TempEnable, bool BattEnable, uint16_t LogInterval)
02524 {
02525 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_SETLOGMODE;
02526 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02527 tagop->u.gen2.u.custom.u.ids.u.setLogMode.AccessPassword = accessPassword;
02528 tagop->u.gen2.u.custom.u.ids.u.setLogMode.CommandCode = 0xA1;
02529 tagop->u.gen2.u.custom.u.ids.u.setLogMode.Password = password;
02530 tagop->u.gen2.u.custom.u.ids.u.setLogMode.sl900A.level = level;
02531 tagop->u.gen2.u.custom.u.ids.u.setLogMode.sl900A.dataLog = form;
02532 tagop->u.gen2.u.custom.u.ids.u.setLogMode.sl900A.rule = rule;
02533 tagop->u.gen2.u.custom.u.ids.u.setLogMode.Ext1Enable = Ext1Enable;
02534 tagop->u.gen2.u.custom.u.ids.u.setLogMode.Ext2Enable = Ext2Enable;
02535 tagop->u.gen2.u.custom.u.ids.u.setLogMode.TempEnable = TempEnable;
02536 tagop->u.gen2.u.custom.u.ids.u.setLogMode.BattEnable = BattEnable;
02537 tagop->u.gen2.u.custom.u.ids.u.setLogMode.LogInterval = LogInterval;
02538
02539 return TMR_SUCCESS;
02540 }
02541
02549 TMR_Status
02550 TMR_TagOp_init_GEN2_IDS_SL900A_EndLog(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword,
02551 PasswordLevel level, uint32_t password)
02552 {
02553 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_ENDLOG;
02554 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02555 tagop->u.gen2.u.custom.u.ids.u.endLog.AccessPassword = accessPassword;
02556 tagop->u.gen2.u.custom.u.ids.u.endLog.CommandCode = 0xA6;
02557 tagop->u.gen2.u.custom.u.ids.u.endLog.Password = password;
02558 tagop->u.gen2.u.custom.u.ids.u.endLog.sl900A.level = level;
02559
02560 return TMR_SUCCESS;
02561 }
02562
02575 TMR_Status
02576 TMR_TagOp_init_GEN2_IDS_SL900A_Initialize(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword,
02577 PasswordLevel level, uint32_t password, uint8_t delayMode,
02578 uint16_t delayTime, bool timeEnable, uint16_t numberOfWords,
02579 uint8_t BrokenWordPointer)
02580 {
02581 uint16_t mask = 0x1 << 1;
02582
02583 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_INITIALIZE;
02584 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02585 tagop->u.gen2.u.custom.u.ids.u.initialize.AccessPassword = accessPassword;
02586 tagop->u.gen2.u.custom.u.ids.u.initialize.CommandCode = 0xAC;
02587 tagop->u.gen2.u.custom.u.ids.u.initialize.Password = password;
02588 tagop->u.gen2.u.custom.u.ids.u.initialize.sl900A.level = level;
02589
02590 if (TMR_GEN2_IDS_SL900A_DELAYMODE_TIMER == delayMode)
02591 {
02592 uint16_t raw = 0;
02593 raw &= (uint16_t)~mask;
02594 tagop->u.gen2.u.custom.u.ids.u.initialize.delayTime.raw = raw;
02595 tagop->u.gen2.u.custom.u.ids.u.initialize.delayTime.Mode = (DelayMode)delayMode;
02596 }
02597 else
02598 {
02599 tagop->u.gen2.u.custom.u.ids.u.initialize.delayTime.raw |= mask;
02600 tagop->u.gen2.u.custom.u.ids.u.initialize.delayTime.Mode = (DelayMode)delayMode;
02601 }
02602
02603 if (delayTime)
02604 {
02605 uint16_t maskDelayTime = 0xFFF << 4;
02606 tagop->u.gen2.u.custom.u.ids.u.initialize.delayTime.raw &= (uint16_t)~maskDelayTime;
02607 tagop->u.gen2.u.custom.u.ids.u.initialize.delayTime.raw |= (uint16_t)(delayTime << 4);
02608 tagop->u.gen2.u.custom.u.ids.u.initialize.delayTime.Time = delayTime;
02609 }
02610 mask = 0x1;
02611 if(timeEnable)
02612 {
02613 tagop->u.gen2.u.custom.u.ids.u.initialize.delayTime.raw |= mask;
02614 tagop->u.gen2.u.custom.u.ids.u.initialize.delayTime.IrqTimerEnable = timeEnable;
02615 }
02616 else
02617 {
02618 tagop->u.gen2.u.custom.u.ids.u.initialize.delayTime.raw &= (uint16_t)~mask;
02619 tagop->u.gen2.u.custom.u.ids.u.initialize.delayTime.IrqTimerEnable = timeEnable;
02620 }
02621
02622 mask = 0x1FF;
02623 if (numberOfWords)
02624 {
02625 tagop->u.gen2.u.custom.u.ids.u.initialize.applicationData.raw &= (uint16_t)~mask;
02626 tagop->u.gen2.u.custom.u.ids.u.initialize.applicationData.raw |= (uint16_t)(numberOfWords << 7);
02627 tagop->u.gen2.u.custom.u.ids.u.initialize.applicationData.NumberOfWords = numberOfWords;
02628 }
02629
02630 mask = 0x7;
02631 if (BrokenWordPointer)
02632 {
02633 tagop->u.gen2.u.custom.u.ids.u.initialize.applicationData.raw &= (uint16_t)~mask;
02634 tagop->u.gen2.u.custom.u.ids.u.initialize.applicationData.raw |= (uint16_t)(BrokenWordPointer);
02635 tagop->u.gen2.u.custom.u.ids.u.initialize.applicationData.BrokenWordPointer = BrokenWordPointer;
02636 }
02637
02638 return TMR_SUCCESS;
02639 }
02640
02641
02649 TMR_Status
02650 TMR_TagOp_init_GEN2_IDS_SL900A_AccessFifoStatus(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword,
02651 PasswordLevel level, uint32_t password)
02652 {
02653 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_ACCESSFIFOSTATUS;
02654 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02655 tagop->u.gen2.u.custom.u.ids.u.accessFifoStatus.status.AccessPassword = accessPassword;
02656 tagop->u.gen2.u.custom.u.ids.u.accessFifoStatus.status.CommandCode = 0xAF;
02657 tagop->u.gen2.u.custom.u.ids.u.accessFifoStatus.status.Password = password;
02658 tagop->u.gen2.u.custom.u.ids.u.accessFifoStatus.status.sl900A.level = level;
02659 tagop->u.gen2.u.custom.u.ids.u.accessFifoStatus.status.operation = TMR_GEN2_IDS_SL900A_ACCESSFIFO_STATUS;
02660
02661 return TMR_SUCCESS;
02662 }
02663
02672 TMR_Status
02673 TMR_TagOp_init_GEN2_IDS_SL900A_AccessFifoRead(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword,
02674 PasswordLevel level, uint32_t password, uint8_t readLength)
02675 {
02676 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_ACCESSFIFOREAD;
02677 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02678 tagop->u.gen2.u.custom.u.ids.u.accessFifoRead.read.AccessPassword = accessPassword;
02679 tagop->u.gen2.u.custom.u.ids.u.accessFifoRead.read.CommandCode = 0xAF;
02680 tagop->u.gen2.u.custom.u.ids.u.accessFifoRead.read.Password = password;
02681 tagop->u.gen2.u.custom.u.ids.u.accessFifoRead.read.sl900A.level = level;
02682 tagop->u.gen2.u.custom.u.ids.u.accessFifoRead.read.operation = TMR_GEN2_IDS_SL900A_ACCESSFIFO_READ;
02683
02684 if (readLength != (readLength & 0xF))
02685 {
02686 return TMR_ERROR_MSG_INVALID_PARAMETER_VALUE;
02687 }
02688 tagop->u.gen2.u.custom.u.ids.u.accessFifoRead.length = readLength;
02689
02690 return TMR_SUCCESS;
02691 }
02692
02701 TMR_Status
02702 TMR_TagOp_init_GEN2_IDS_SL900A_AccessFifoWrite(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword,
02703 PasswordLevel level, uint32_t password, TMR_uint8List *payLoad)
02704 {
02705 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_ACCESSFIFOWRITE;
02706 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02707 tagop->u.gen2.u.custom.u.ids.u.accessFifoWrite.write.AccessPassword = accessPassword;
02708 tagop->u.gen2.u.custom.u.ids.u.accessFifoWrite.write.CommandCode = 0xAF;
02709 tagop->u.gen2.u.custom.u.ids.u.accessFifoWrite.write.Password = password;
02710 tagop->u.gen2.u.custom.u.ids.u.accessFifoWrite.write.sl900A.level = level;
02711 tagop->u.gen2.u.custom.u.ids.u.accessFifoWrite.write.operation = TMR_GEN2_IDS_SL900A_ACCESSFIFO_WRITE;
02712
02713 if (payLoad->len != (payLoad->len & 0xF))
02714 {
02715 return TMR_ERROR_MSG_INVALID_PARAMETER_VALUE;
02716 }
02717 tagop->u.gen2.u.custom.u.ids.u.accessFifoWrite.payLoad = payLoad;
02718
02719 return TMR_SUCCESS;
02720 }
02721
02730 TMR_Status
02731 TMR_TagOp_init_GEN2_IDS_SL900A_StartLog(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword,
02732 PasswordLevel level, uint32_t password, TMR_TimeStructure *timestamp)
02733 {
02734 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_STARTLOG;
02735 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02736 tagop->u.gen2.u.custom.u.ids.u.startLog.AccessPassword = accessPassword;
02737 tagop->u.gen2.u.custom.u.ids.u.startLog.CommandCode = 0xA7;
02738 tagop->u.gen2.u.custom.u.ids.u.startLog.Password = password;
02739 tagop->u.gen2.u.custom.u.ids.u.startLog.sl900A.level = level;
02740 if (NULL == timestamp)
02741 {
02745 return TMR_ERROR_TIMESTAMP_NULL;
02746 }
02747
02748 tagop->u.gen2.u.custom.u.ids.u.startLog.startTime = 0;
02749 tagop->u.gen2.u.custom.u.ids.u.startLog.startTime |= (uint32_t)((timestamp->tm_year - 2010) << 26);
02750 tagop->u.gen2.u.custom.u.ids.u.startLog.startTime |= (uint32_t)((timestamp->tm_mon) << 22);
02751 tagop->u.gen2.u.custom.u.ids.u.startLog.startTime |= (uint32_t)(timestamp->tm_mday << 17);
02752 tagop->u.gen2.u.custom.u.ids.u.startLog.startTime |= (uint32_t)(timestamp->tm_hour << 12);
02753 tagop->u.gen2.u.custom.u.ids.u.startLog.startTime |= (uint32_t)(timestamp->tm_min << 6);
02754 tagop->u.gen2.u.custom.u.ids.u.startLog.startTime |= (uint32_t)(timestamp->tm_sec);
02755
02756 return TMR_SUCCESS;
02757 }
02758
02767 TMR_Status
02768 TMR_TagOp_init_GEN2_IDS_SL900A_GetBatteryLevel(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword,
02769 PasswordLevel level, uint32_t password, BatteryType type)
02770 {
02771 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_GETBATTERYLEVEL;
02772 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02773 tagop->u.gen2.u.custom.u.ids.u.batteryLevel.AccessPassword = accessPassword;
02774 tagop->u.gen2.u.custom.u.ids.u.batteryLevel.CommandCode = 0xAA;
02775 tagop->u.gen2.u.custom.u.ids.u.batteryLevel.Password = password;
02776 tagop->u.gen2.u.custom.u.ids.u.batteryLevel.sl900A.level = level;
02777 tagop->u.gen2.u.custom.u.ids.u.batteryLevel.batteryType = type;
02778
02779 return TMR_SUCCESS;
02780 }
02781
02790 TMR_Status
02791 TMR_TagOp_init_GEN2_IDS_SL900A_SetLogLimit(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword, PasswordLevel level,
02792 uint32_t password, LogLimits *logLimits)
02793 {
02794 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_SETLOGLIMITS;
02795 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02796 tagop->u.gen2.u.custom.u.ids.u.setLogLimit.AccessPassword = accessPassword;
02797 tagop->u.gen2.u.custom.u.ids.u.setLogLimit.CommandCode = 0xA2;
02798 tagop->u.gen2.u.custom.u.ids.u.setLogLimit.Password = password;
02799 tagop->u.gen2.u.custom.u.ids.u.setLogLimit.sl900A.level = level;
02800
02804 if (0x03FF < logLimits->extremeLower)
02805 {
02806 return TMR_ERROR_MSG_INVALID_PARAMETER_VALUE;
02807 }
02808
02809 tagop->u.gen2.u.custom.u.ids.u.setLogLimit.limit.extremeLower = logLimits->extremeLower;
02810
02811 if (0x03FF < logLimits->lower)
02812 {
02813 return TMR_ERROR_MSG_INVALID_PARAMETER_VALUE;
02814 }
02815 tagop->u.gen2.u.custom.u.ids.u.setLogLimit.limit.lower = logLimits->lower;
02816
02817 if (0x03FF < logLimits->upper)
02818 {
02819 return TMR_ERROR_MSG_INVALID_PARAMETER_VALUE;
02820 }
02821 tagop->u.gen2.u.custom.u.ids.u.setLogLimit.limit.upper = logLimits->upper;
02822
02823 if (0x03FF < logLimits->extremeUpper)
02824 {
02825 return TMR_ERROR_MSG_INVALID_PARAMETER_VALUE;
02826 }
02827 tagop->u.gen2.u.custom.u.ids.u.setLogLimit.limit.extremeUpper = logLimits->extremeUpper;
02828
02829 return TMR_SUCCESS;
02830
02831 }
02832
02841 TMR_Status
02842 TMR_TagOp_init_GEN2_IDS_SL900A_ShelfLifeBlock0(TMR_TagOp_GEN2_IDS_SL900A_ShelfLifeBlock0 *block0,
02843 uint8_t tmax, uint8_t tmin, uint8_t tstd, uint8_t ea)
02844 {
02845 uint64_t mask;
02846 block0->raw = 0;
02847
02848
02849 {
02850 block0->Tmax = tmax;
02851 mask = TMR_makeBitMask(24, 8);
02852 block0->raw &= ~mask;
02853 block0->raw |= (uint32_t)((uint32_t)tmax << 24);
02854 }
02855
02856
02857 {
02858 block0->Tmin = tmin;
02859 mask = TMR_makeBitMask(16, 8);
02860 block0->raw &= ~mask;
02861 block0->raw |= (uint32_t)((uint32_t)tmin << 16);
02862 }
02863
02864
02865 {
02866 block0->Tstd = tstd;
02867 mask = TMR_makeBitMask(8, 8);
02868 block0->raw &= ~mask;
02869 block0->raw |= (uint32_t)((uint32_t)tstd << 8);
02870 }
02871
02872
02873 {
02874 block0->Ea = ea;
02875 mask = TMR_makeBitMask(0, 8);
02876 block0->raw &= ~mask;
02877 block0->raw |= (uint32_t)((uint32_t)ea << 0);
02878 }
02879
02880 return TMR_SUCCESS;
02881 }
02882
02883
02893 TMR_Status
02894 TMR_TagOp_init_GEN2_IDS_SL900A_ShelfLifeBlock1(TMR_TagOp_GEN2_IDS_SL900A_ShelfLifeBlock1 *block1,
02895 uint16_t slinit, uint16_t tint, uint8_t sensorid,
02896 bool negative, bool algorithm)
02897 {
02898 uint64_t mask;
02899 block1->raw = 0;
02900
02901
02902 {
02903 block1->SLinit = slinit;
02904 mask = TMR_makeBitMask(16, 16);
02905 block1->raw &= ~mask;
02906 block1->raw |= (uint32_t)((uint32_t)slinit << 16);
02907 }
02908
02909
02910 {
02911 block1->Tint = tint;
02912 mask = TMR_makeBitMask(6, 10);
02913 block1->raw &= ~mask;
02914 block1->raw |= (uint32_t)((uint32_t)tint << 6);
02915 }
02916
02917
02918 {
02919 block1->sensorID = sensorid;
02920 mask = TMR_makeBitMask(4, 2);
02921 block1->raw &= ~mask;
02922 block1->raw |= (uint32_t)((uint32_t)sensorid << 4);
02923 }
02924
02925
02926 {
02927 block1->enableNegative = negative;
02928 mask = TMR_makeBitMask(3, 1);
02929 block1->raw &= ~mask;
02930 block1->raw |= (uint32_t)(negative << 3);
02931 }
02932
02933
02934 {
02935 block1->algorithmEnable = algorithm;
02936 mask = TMR_makeBitMask(2, 1);
02937 block1->raw &= ~mask;
02938 block1->raw |= (uint32_t)(negative << 2);
02939 }
02940
02941
02942 block1->rfu = 0;
02943 mask = TMR_makeBitMask(0, 2);
02944 block1->raw &= ~mask;
02945 block1->raw |= (uint32_t)(0 << 0);
02946
02947 return TMR_SUCCESS;
02948 }
02949
02959 TMR_Status
02960 TMR_TagOp_init_GEN2_IDS_SL900A_SetShelfLife(TMR_TagOp *tagop, TMR_GEN2_Password accessPassword, PasswordLevel level,
02961 uint32_t password,TMR_TagOp_GEN2_IDS_SL900A_ShelfLifeBlock0 *block0,
02962 TMR_TagOp_GEN2_IDS_SL900A_ShelfLifeBlock1 *block1)
02963 {
02964 tagop->type = TMR_TAGOP_GEN2_IDS_SL900A_SETSHELFLIFE;
02965 tagop->u.gen2.u.custom.chipType = TMR_SR_GEN2_IDS_SL900A_SILICON;
02966 tagop->u.gen2.u.custom.u.ids.u.setShelfLife.AccessPassword = accessPassword;
02967 tagop->u.gen2.u.custom.u.ids.u.setShelfLife.CommandCode = 0xAB;
02968 tagop->u.gen2.u.custom.u.ids.u.setShelfLife.Password = password;
02969 tagop->u.gen2.u.custom.u.ids.u.setShelfLife.sl900A.level = level;
02970 tagop->u.gen2.u.custom.u.ids.u.setShelfLife.shelfLifeBlock0 = block0;
02971 tagop->u.gen2.u.custom.u.ids.u.setShelfLife.shelfLifeBlock1 = block1;
02972
02973 return TMR_SUCCESS;
02974 }
02975
02981 TMR_Status
02982 TMR_init_UserConfigOp(TMR_SR_UserConfigOp *config, TMR_SR_UserConfigOperation op)
02983 {
02984 config->category = TMR_SR_ALL;
02985 config->op = op;
02986
02987 return TMR_SUCCESS;
02988 }
02989
02996 TMR_Status
02997 TMR_init_GEN2_NXP_G2I_ConfigWord(TMR_NXP_ConfigWord *configWord)
02998 {
02999 configWord->data = 0x0000;
03000 return TMR_SUCCESS;
03001 }
03002
03009 TMR_Status
03010 TMR_init_GEN2_Impinj_Monza4_ControlByte(TMR_Monza4_ControlByte *controlByte)
03011 {
03012 controlByte->data = 0x00;
03013 return TMR_SUCCESS;
03014 }
03015
03022 TMR_Status
03023 TMR_init_GEN2_Impinj_Monza4_Payload(TMR_Monza4_Payload *payload)
03024 {
03025 payload->data = 0x0000;
03026 return TMR_SUCCESS;
03027 }
03028
03032 TMR_Status
03033 TMR_update_GEN2_IDS_SL900A_SfeParameters(TMR_TagOp_GEN2_IDS_SL900A_SfeParameters *sfe)
03034 {
03035 uint64_t mask;
03036
03037 switch (sfe->type)
03038 {
03039 case TMR_GEN2_IDS_SL900A_SFE_RANG:
03040 {
03041 mask = TMR_makeBitMask(11, 5);
03042 sfe->raw &= ~mask;
03043 sfe->raw |= ((uint64_t)(((uint64_t)sfe->Rang) << 11));
03044
03045 break;
03046 }
03047 case TMR_GEN2_IDS_SL900A_SFE_SETI:
03048 {
03049 mask = TMR_makeBitMask(6, 5);
03050 sfe->raw &= ~mask;
03051 sfe->raw |= ((uint64_t)(((uint64_t)sfe->Seti) << 6));
03052
03053 break;
03054 }
03055 case TMR_GEN2_IDS_SL900A_SFE_EXT1:
03056 {
03057 mask = TMR_makeBitMask(4, 2);
03058 sfe->raw &= ~mask;
03059 sfe->raw |= ((uint64_t)(((uint64_t)sfe->Ext1) << 4));
03060
03061 break;
03062 }
03063 case TMR_GEN2_IDS_SL900A_SFE_EXT2:
03064 {
03065 mask = TMR_makeBitMask(3, 1);
03066 sfe->raw &= ~mask;
03067 sfe->raw |= ((uint64_t)(((uint64_t)sfe->Ext2) << 3));
03068
03069 break;
03070 }
03071 case TMR_GEN2_IDS_SL900A_SFE_AUTORANGEDISABLE:
03072 {
03073 mask = TMR_makeBitMask(2, 1);
03074 sfe->raw &= ~mask;
03075 sfe->raw |= ((uint64_t)(((uint64_t)sfe->AutorangeDisable) << 2));
03076
03077 break;
03078 }
03079 case TMR_GEN2_IDS_SL900A_SFE_VERIFYSENSORID:
03080 {
03081 mask = TMR_makeBitMask(0, 2);
03082 sfe->raw &= ~mask;
03083 sfe->raw |= ((uint64_t)(((uint64_t)sfe->VerifySensorID) << 0));
03084
03085 break;
03086 }
03087 default:
03088 break;
03089 }
03090 return TMR_SUCCESS;
03091 }
03092
03096 TMR_Status
03097 TMR_update_GEN2_IDS_SL900A_CalibrationData(TMR_TagOp_GEN2_IDS_SL900A_CalibrationData *cal)
03098 {
03099 uint64_t mask;
03100
03101 switch (cal->type)
03102 {
03103 case TMR_GEN2_IDS_SL900A_CALIBRATION_COARSE1:
03104 {
03105 mask = TMR_makeBitMask(48, 3);
03106 cal->raw &= ~mask;
03107 cal->raw |= ((uint64_t)(((uint64_t)cal->Coarse1) << 48));
03108 cal->raw = cal->raw;
03109
03110 break;
03111 }
03112 case TMR_GEN2_IDS_SL900A_CALIBRATION_COARSE2:
03113 {
03114 mask = TMR_makeBitMask(40, 3);
03115 cal->raw &= ~mask;
03116 cal->raw |= ((uint64_t)(((uint64_t)cal->Coarse2) << 40));
03117 cal->raw = cal->raw;
03118
03119 break;
03120 }
03121 case TMR_GEN2_IDS_SL900A_CALIBRATION_GNDSWITCH:
03122 {
03123 mask = TMR_makeBitMask(39, 1);
03124 cal->raw &= ~mask;
03125 cal->raw |= ((uint64_t)(((uint64_t)cal->GndSwitch) << 39));
03126 cal->raw = cal->raw;
03127
03128 break;
03129 }
03130 case TMR_GEN2_IDS_SL900A_CALIBRATION_SELP12:
03131 {
03132 mask = TMR_makeBitMask(37, 2);
03133 cal->raw &= ~mask;
03134 cal->raw |= ((uint64_t)(((uint64_t)cal->Selp12) << 37));
03135 cal->raw = cal->raw;
03136
03137 break;
03138 }
03139 case TMR_GEN2_IDS_SL900A_CALIBRATION_DF:
03140 {
03141 mask = TMR_makeBitMask(24, 8);
03142 cal->raw &= ~mask;
03143 cal->raw |= ((uint64_t)(((uint64_t)cal->Df) << 24));
03144 cal->raw = cal->raw;
03145
03146 break;
03147 }
03148 case TMR_GEN2_IDS_SL900A_CALIBRATION_SWEXTEN:
03149 {
03150 mask = TMR_makeBitMask(23, 1);
03151 cal->raw &= ~mask;
03152 cal->raw |= ((uint64_t)(((uint64_t)cal->SwExtEn) << 23));
03153 cal->raw = cal->raw;
03154
03155 break;
03156 }
03157 case TMR_GEN2_IDS_SL900A_CALIBRATION_SELP22:
03158 {
03159 mask = TMR_makeBitMask(21, 2);
03160 cal->raw &= ~mask;
03161 cal->raw |= ((uint64_t)(((uint64_t)cal->Selp22) << 21));
03162 cal->raw = cal->raw;
03163
03164 break;
03165 }
03166 case TMR_GEN2_IDS_SL900A_CALIBRATION_IRLEV:
03167 {
03168 mask = TMR_makeBitMask(19, 2);
03169 cal->raw &= ~mask;
03170 cal->raw |= ((uint64_t)(((uint64_t)cal->Irlev) << 19));
03171 cal->raw = cal->raw;
03172
03173 break;
03174 }
03175 case TMR_GEN2_IDS_SL900A_CALIBRATION_EXCRES:
03176 {
03177 mask = TMR_makeBitMask(2, 1);
03178 cal->raw &= ~mask;
03179 cal->raw |= ((uint64_t)(((uint64_t)cal->ExcRes) << 2));
03180 cal->raw = cal->raw;
03181
03182 break;
03183 }
03184 default:
03185 break;
03186 }
03187 return TMR_SUCCESS;
03188 }
03189
03193 TMR_Status
03194 TMR_init_GEN2_IDS_SL900A_CalibrationData(uint8_t byte[7], TMR_TagOp_GEN2_IDS_SL900A_CalibrationData *cal)
03195 {
03196 if (NULL != byte)
03197 {
03202 uint8_t tmp[] = {0,0,0,0,0,0,0,0,};
03203 memcpy(tmp+1, byte, 7);
03204 cal->raw = (uint64_t)(0
03205 | ((uint64_t)(tmp[ 0]) << 56)
03206 | ((uint64_t)(tmp[ 1]) << 48)
03207 | ((uint64_t)(tmp[ 2]) << 40)
03208 | ((uint64_t)(tmp[3]) << 32)
03209 | ((uint64_t)(tmp[4]) << 24)
03210 | ((uint64_t)(tmp[5]) << 16)
03211 | ((uint64_t)(tmp[ 6]) << 8)
03212 | ((uint64_t)(tmp[7]) << 0));
03213
03214 cal->raw &= (uint64_t)0x00FFFFFFFFFFFFFFLL;
03215 }
03216
03217 return TMR_SUCCESS;
03218 }
03219
03223 TMR_Status
03224 TMR_init_GEN2_IDS_SL900A_SfeParameters(uint8_t byte[2], TMR_TagOp_GEN2_IDS_SL900A_SfeParameters *sfe)
03225 {
03226
03227 int hi, lo;
03228 hi = (uint16_t)(byte[0]) << 8;
03229 lo = (uint16_t)(byte[1]);
03230 sfe->raw = (hi | lo);
03231
03232 return TMR_SUCCESS;
03233 }
03234
03241 TMR_Status
03242 TMR_init_GEN2_IDS_SL900A_SensorReading(TMR_uint8List *reply, TMR_TagOp_GEN2_IDS_SL900A_SensorReading *sensor)
03243 {
03244
03245 if (2 != reply->len)
03246 {
03247
03248 return TMR_ERROR_MSG_INVALID_PARAMETER_VALUE;
03249 }
03250 sensor->reply = reply->list[0] << 8 | reply->list[1];
03251 sensor->Raw = sensor->reply;
03252 sensor->ADError = (((sensor->reply >> 15) & 0x1) != 0);
03253 sensor->RangeLimit = (uint8_t) ((sensor->reply >> 10) & 0x1F);
03254 sensor->Value = ((sensor->reply >> 0 ) & 0x3FF);
03255
03256 return TMR_SUCCESS;
03257 }
03258
03265 TMR_Status
03266 TMR_init_GEN2_IDS_SL900A_CalSfe(TMR_uint8List *reply, TMR_TagOp_GEN2_IDS_SL900A_CalSfe *calSfe)
03267 {
03268 uint64_t mask;
03269 TMR_init_GEN2_IDS_SL900A_CalibrationData(reply->list, &calSfe->Cal);
03270 TMR_init_GEN2_IDS_SL900A_SfeParameters(reply->list + 7, &calSfe->Sfe);
03271
03272 mask = TMR_makeBitMask(51, 5);
03273 calSfe->Cal.Ad1 = (uint8_t)((calSfe->Cal.raw & mask) >> 51);
03274
03275 mask = TMR_makeBitMask(48, 3);
03276 calSfe->Cal.Coarse1 = (uint8_t)((calSfe->Cal.raw & mask) >> 48);
03277
03278 mask = TMR_makeBitMask(43, 5);
03279 calSfe->Cal.Ad2 = (uint8_t)((calSfe->Cal.raw & mask) >> 43);
03280
03281 mask = TMR_makeBitMask(40, 3);
03282 calSfe->Cal.Coarse2 = (uint8_t)((calSfe->Cal.raw & mask) >> 40);
03283
03284 mask = TMR_makeBitMask(39, 1);
03285 calSfe->Cal.GndSwitch = (uint8_t)((calSfe->Cal.raw & mask) >> 39);
03286
03287 mask = TMR_makeBitMask(37, 2);
03288 calSfe->Cal.Selp12 = (uint8_t)((calSfe->Cal.raw & mask) >> 37);
03289
03290 mask = TMR_makeBitMask(32, 5);
03291 calSfe->Cal.Adf = (uint8_t)((calSfe->Cal.raw & mask) >> 32);
03292
03293 mask = TMR_makeBitMask(24, 8);
03294 calSfe->Cal.Df = (uint8_t)((calSfe->Cal.raw & mask) >> 24);
03295
03296 mask = TMR_makeBitMask(23, 1);
03297 calSfe->Cal.SwExtEn = (uint8_t)((calSfe->Cal.raw & mask) >> 23);
03298
03299 mask = TMR_makeBitMask(21, 2);
03300 calSfe->Cal.Selp22 = (uint8_t)((calSfe->Cal.raw & mask) >> 21);
03301
03302 mask = TMR_makeBitMask(19, 2);
03303 calSfe->Cal.Irlev = (uint8_t)((calSfe->Cal.raw & mask) >> 19);
03304
03305 mask = TMR_makeBitMask(14, 5);
03306 calSfe->Cal.RingCal = (uint8_t)((calSfe->Cal.raw & mask) >> 14);
03307
03308 mask = TMR_makeBitMask(7, 7);
03309 calSfe->Cal.OffInt = (uint8_t)((calSfe->Cal.raw & mask) >> 7);
03310
03311 mask = TMR_makeBitMask(3, 4);
03312 calSfe->Cal.Reftc = (uint8_t)((calSfe->Cal.raw & mask) >> 3);
03313
03314 mask = TMR_makeBitMask(2, 1);
03315 calSfe->Cal.ExcRes = (uint8_t)((calSfe->Cal.raw & mask) >> 2);
03316
03317 mask = TMR_makeBitMask(0, 2);
03318 calSfe->Cal.RFU = (uint8_t)((calSfe->Cal.raw & mask) >> 0);
03319
03320 mask = TMR_makeBitMask(11, 5);
03321 calSfe->Sfe.Rang = (uint8_t)((calSfe->Sfe.raw & mask) >> 11);
03322
03323 mask = TMR_makeBitMask(6, 5);
03324 calSfe->Sfe.Seti = (uint8_t)((calSfe->Sfe.raw & mask) >> 6);
03325
03326 mask = TMR_makeBitMask(4, 2);
03327 calSfe->Sfe.Ext1 = (uint8_t)((calSfe->Sfe.raw & mask) >> 4);
03328
03329 mask = TMR_makeBitMask(3, 1);
03330 calSfe->Sfe.Ext2 = (uint8_t)((calSfe->Sfe.raw & mask) >> 3);
03331
03332 mask = TMR_makeBitMask(2, 1);
03333 calSfe->Sfe.AutorangeDisable = (uint8_t)((calSfe->Sfe.raw & mask) >> 2);
03334
03335 mask = TMR_makeBitMask(0, 2);
03336 calSfe->Sfe.VerifySensorID = (uint8_t)((calSfe->Sfe.raw & mask) >> 0);
03337
03338 return TMR_SUCCESS;
03339 }
03340
03348 TMR_Status
03349 TMR_init_GEN2_IDS_SL900A_BatteryLevelReading(TMR_uint8List *reply, TMR_TagOp_GEN2_IDS_SL900A_BatteryLevelReading *battery)
03350 {
03351
03352 if (2 != reply->len)
03353 {
03354
03355 return TMR_ERROR_MSG_INVALID_PARAMETER_VALUE;
03356 }
03357 battery->reply = (uint16_t)(reply->list[0] << 8 | reply->list[1]);
03358 battery->ADError = (bool)(((battery->reply >> 15) & 0x1) != 0);
03359 battery->BatteryType = (uint8_t) ((battery->reply >> 14) & 0x1);
03360 battery->Value = (uint16_t)((battery->reply >> 0 ) & 0x3FF);
03361
03362 return TMR_SUCCESS;
03363 }
03370 TMR_Status
03371 TMR_init_GEN2_IDS_SL900A_FifoStatus(TMR_uint8List *statusReply, TMR_TagOp_GEN2_IDS_SL900A_FifoStatus *status)
03372 {
03373
03374 uint8_t reply;
03375 if (1 != statusReply->len)
03376 {
03377
03378 return TMR_ERROR_MSG_INVALID_PARAMETER_VALUE;
03379 }
03380 status->raw = statusReply->list[0];
03381 reply = statusReply->list[0];
03382 status->fifoBusy = (0 != ((reply >> 7) & 1));
03383 status->dataReady = (0 != ((reply >> 6) & 1));
03384 status->noData = (0 != ((reply >> 5) & 1));
03385 status->numValidBytes = (uint8_t)(reply & 0xF);
03386
03387 return TMR_SUCCESS;
03388 }
03389
03396 TMR_Status
03397 TMR_init_GEN2_IDS_SL900A_LogState(TMR_uint8List *reply, TMR_TagOp_GEN2_IDS_SL900A_LogState *log)
03398 {
03399
03400 uint32_t offset = 0;
03401 uint32_t raw;
03402 if ((9 != reply->len) && (20 != reply->len))
03403 {
03404
03405 return TMR_ERROR_MSG_INVALID_PARAMETER_VALUE;
03406 }
03407
03408 if (9 == reply->len)
03409 {
03410 log->limitCount.extremeLower = reply->list[offset + 0];
03411 log->limitCount.lower = reply->list[offset + 1];
03412 log->limitCount.upper = reply->list[offset + 2];
03413 log->limitCount.extremeUpper = reply->list[offset + 3];
03414
03415 offset += 4;
03416 raw = TMR_byteArrayToInt(reply->list, offset);
03417 log->statStatus.MeasurementAddressPointer = (uint16_t)((raw >> 22) & 0x1FF);
03418 log->statStatus.NumMemReplacements = (uint8_t) ((raw >> 16) & 0x3F);
03419 log->statStatus.NumMeasurements = (uint16_t) ((raw >> 1) & 0x7FFF);
03420 log->statStatus.Active = (bool)(0 != (raw & 0x1));
03421 offset += 4;
03422 }
03423 if (20 == reply->len)
03424 {
03425
03426 offset += 8;
03427 offset += 4;
03428 }
03429 raw = TMR_byteArrayToInt(reply->list, offset);
03430 log->statFlag.Active = (bool)(0 != ((raw >> 7) & 1));
03431 log->statFlag.Full = (bool)(0 != ((raw >> 6) & 1));
03432 log->statFlag.Overwritten = (bool)(0 != ((raw >> 5) & 1));
03433 log->statFlag.ADError = (bool) (0 != ((raw >> 4) & 1));
03434 log->statFlag.LowBattery = (bool) (0 != ((raw >> 3) & 1));
03435 log->statFlag.ShelfLifeLow = (bool) (0 != ((raw >> 2) & 1));
03436 log->statFlag.ShelfLifeHigh = (bool)(0 != ((raw >> 1) & 1));
03437 log->statFlag.ShelfLifeExpired = (bool)(0 != ((raw >> 0) & 1));
03438
03439 return TMR_SUCCESS;
03440 }
03441
03449 TMR_Status
03450 TMR_init_GEN2_IDS_SL900A_MeasurementSetupData(TMR_uint8List *reply, TMR_TagOp_GEN2_IDS_SL900A_MeasurementSetupData *measurement)
03451 {
03452 if(16 != reply->len)
03453 {
03454
03455 return TMR_ERROR_MSG_INVALID_PARAMETER_VALUE;
03456 }
03457
03458 memcpy(measurement->Raw, reply->list, reply->len);
03459
03460
03461 {
03462 uint32_t temp;
03463 temp = TMR_byteArrayToInt(reply->list, 0);
03464 measurement->startTime.tm_year = (int)(2010+((temp >> 26) & 0x3F));
03465 measurement->startTime.tm_mon = (int)((temp >> 22) & 0xF);
03466 measurement->startTime.tm_mday = (int)((temp >> 17) & 0x1F);
03467 measurement->startTime.tm_hour = (int)((temp >> 12) & 0x1F);
03468 measurement->startTime.tm_min = (int)((temp >> 6) & 0x3F);
03469 measurement->startTime.tm_sec = (int)((temp >> 0) & 0x3F);
03470 }
03471
03472 {
03473 int offset = 4;
03474 uint64_t value = 0;
03475
03476
03477
03478 value = TMR_byteArrayToLong(reply->list, offset);
03479
03480
03481
03482
03483 measurement->loglimit.extremeLower = (uint16_t) ((value >> 54) & 0x03FF);
03484 measurement->loglimit.lower = (uint16_t) ((value >> 44) & 0x03FF);
03485 measurement->loglimit.upper = (uint16_t) ((value >> 34) & 0x03FF);
03486 measurement->loglimit.extremeUpper = (uint16_t) ((value >> 24) & 0x03FF);
03487 }
03488
03489 {
03490 uint8_t temp = (uint8_t)reply->list[9];
03491 measurement->logModeData.Raw = temp;
03492 measurement->logModeData.Form = (LoggingForm)((temp >> 5) & 7);
03493 measurement->logModeData.Storage = (StorageRule)(((temp >> 4) & 1));
03494 measurement->logModeData.Ext1Enable = (0 != ((temp >> 3) & 1));
03495 measurement->logModeData.Ext2Enable = (0 != ((temp >> 2) & 1));
03496 measurement->logModeData.TempEnable = (0 != ((temp >> 1) & 1));
03497 measurement->logModeData.BattEnable = (0 != ((temp>> 0) & 1));
03498 }
03499
03500 {
03501 uint16_t temp;
03502 temp = TMR_byteArrayToShort(reply->list, 10);
03503 temp = ((temp >> 1) & 0x0001);
03504 measurement->logInterval = temp;
03505 }
03506
03507 {
03508 uint16_t temp;
03509 temp = TMR_byteArrayToShort(reply->list, 12);
03510 measurement->delyTime.raw = temp;
03511 measurement->delyTime.Mode = (0 == ((temp >> 1) & 0x1)) ? TMR_GEN2_IDS_SL900A_DELAYMODE_TIMER
03512 : TMR_GEN2_IDS_SL900A_DELAYMODE_EXTSWITCH;
03513 measurement->delyTime.Time = (uint16_t)((temp >> 4) & 0xFFF);
03514 measurement->delyTime.IrqTimerEnable = (0 != (temp & 0x1));
03515 }
03516
03517 {
03518 uint16_t temp;
03519 temp = TMR_byteArrayToShort(reply->list, 14);
03520 measurement->addData.raw = temp;
03521 measurement->addData.NumberOfWords = (uint16_t)((temp >> 7) & 0x1FF);
03522 measurement->addData.BrokenWordPointer = (uint8_t)(temp & 0x7);
03523 }
03524
03525 return TMR_SUCCESS;
03526 }
03527
03528 #endif
03529 void
03530 TMR_paramProbe(struct TMR_Reader *reader, TMR_Param key)
03531 {
03532
03533
03534
03535
03536 uint32_t buf[] = {0, 0, 0, 0, 0, 0, 0, 0};
03537 TMR_Status ret;
03538
03539 ret = TMR_paramGet(reader, key, &buf);
03540 if (TMR_SUCCESS == ret)
03541 {
03542 if (TMR_READER_TYPE_SERIAL == reader->readerType)
03543 {
03544 BITSET(reader->u.serialReader.paramPresent, key);
03545 BITSET(reader->u.serialReader.paramConfirmed, key);
03546 }
03547 #ifdef TMR_ENABLE_LLRP_READER
03548 if (TMR_READER_TYPE_LLRP == reader->readerType)
03549 {
03550 BITSET(reader->u.llrpReader.paramPresent, key);
03551 BITSET(reader->u.llrpReader.paramConfirmed, key);
03552 }
03553 #endif
03554 }
03555 }
03556
03557
03565 TMR_Status
03566 TMR_paramList(struct TMR_Reader *reader, TMR_Param *keys, uint32_t *len)
03567 {
03568 int i, count, max;
03569
03570 max = *len;
03571 count = 0;
03572 for (i = TMR_PARAM_MIN; i <= TMR_PARAM_MAX ; i++)
03573 {
03574 if (TMR_READER_TYPE_SERIAL == reader->readerType)
03575 {
03576 if (0 == BITGET(reader->u.serialReader.paramConfirmed, i))
03577 {
03578
03579 TMR_paramProbe(reader, (TMR_Param)i);
03580 }
03581
03582 if (BITGET(reader->u.serialReader.paramPresent, i))
03583 {
03584 if (count < max)
03585 keys[count] = (TMR_Param)i;
03586 count++;
03587 }
03588 }
03589 #ifdef TMR_ENABLE_LLRP_READER
03590 if (TMR_READER_TYPE_LLRP == reader->readerType)
03591 {
03592 if (0 == BITGET(reader->u.llrpReader.paramConfirmed, i))
03593 {
03594 TMR_paramProbe(reader, i);
03595 }
03596
03597 if (BITGET(reader->u.llrpReader.paramPresent, i))
03598 {
03599 if (count < max)
03600 keys[count] = i;
03601 count++;
03602 }
03603 }
03604 #endif
03605 }
03606
03607 *len = count;
03608
03609 return TMR_SUCCESS;
03610 }
03611
03612 TMR_Status
03613 TMR_receiveAutonomousReading(struct TMR_Reader *reader, TMR_TagReadData *trd, TMR_Reader_StatsValues *stats)
03614 {
03615 TMR_Status ret;
03616
03617 ret = TMR_SUCCESS;
03618
03619 if (TMR_READER_TYPE_SERIAL != reader->readerType)
03620 {
03621
03622 return TMR_ERROR_UNSUPPORTED;
03623 }
03624
03625 #ifdef TMR_ENABLE_BACKGROUND_READS
03626 {
03630 ret = pthread_create(&reader->autonomousBackgroundReader, NULL,
03631 do_background_receiveAutonomousReading, reader);
03632 if (0 != ret)
03633 {
03634 return TMR_ERROR_NO_THREADS;
03635 }
03636 pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS, NULL);
03637 pthread_setcancelstate(PTHREAD_CANCEL_ENABLE, NULL);
03638 pthread_detach(reader->autonomousBackgroundReader);
03639 }
03640 #else
03641 {
03642
03643 ret = TMR_SR_receiveAutonomousReading(reader, trd, stats);
03644 }
03645 #endif
03646
03647 return ret;
03648 }
03649