00001 /*- 00002 * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting 00003 * All rights reserved. 00004 * 00005 * Redistribution and use in source and binary forms, with or without 00006 * modification, are permitted provided that the following conditions 00007 * are met: 00008 * 1. Redistributions of source code must retain the above copyright 00009 * notice, this list of conditions and the following disclaimer, 00010 * without modification. 00011 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 00012 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 00013 * redistribution must be conditioned upon including a substantially 00014 * similar Disclaimer requirement for further binary redistribution. 00015 * 3. Neither the names of the above-listed copyright holders nor the names 00016 * of any contributors may be used to endorse or promote products derived 00017 * from this software without specific prior written permission. 00018 * 00019 * Alternatively, this software may be distributed under the terms of the 00020 * GNU General Public License ("GPL") version 2 as published by the Free 00021 * Software Foundation. 00022 * 00023 * NO WARRANTY 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 00025 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00026 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 00027 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 00028 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 00029 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 00032 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 00034 * THE POSSIBILITY OF SUCH DAMAGES. 00035 * 00036 */ 00037 00038 /* 00039 * Defintions for the Atheros Wireless LAN controller driver. 00040 */ 00041 #ifndef _DEV_ATH_ATHVAR_H 00042 #define _DEV_ATH_ATHVAR_H 00043 00044 #include <linux/interrupt.h> 00045 #include <linux/list.h> 00046 #include <linux/if_ether.h> 00047 00048 #include "ath5k.h" 00049 #include "debug.h" 00050 00051 #define ATH_RXBUF 40 /* number of RX buffers */ 00052 #define ATH_TXBUF 200 /* number of TX buffers */ 00053 00054 struct ath5k_buf { 00055 struct list_head list; 00056 struct ath5k_desc *desc; /* virtual addr of desc */ 00057 dma_addr_t daddr; /* physical addr of desc */ 00058 struct sk_buff *skb; /* skbuff for buf */ 00059 dma_addr_t skbaddr;/* physical addr of skb data */ 00060 }; 00061 00062 /* 00063 * Data transmit queue state. One of these exists for each 00064 * hardware transmit queue. Packets sent to us from above 00065 * are assigned to queues based on their priority. Not all 00066 * devices support a complete set of hardware transmit queues. 00067 * For those devices the array sc_ac2q will map multiple 00068 * priorities to fewer hardware queues (typically all to one 00069 * hardware queue). 00070 */ 00071 struct ath5k_txq { 00072 unsigned int qnum; /* hardware q number */ 00073 u32 *link; /* link ptr in last TX desc */ 00074 struct list_head q; /* transmit queue */ 00075 spinlock_t lock; /* lock on q and link */ 00076 bool setup; 00077 }; 00078 00079 #define ATH_CHAN_MAX (26+26+26+200+200) 00080 00081 /* Software Carrier, keeps track of the driver state 00082 * associated with an instance of a device */ 00083 struct ath5k_softc { 00084 struct pci_dev *pdev; /* for dma mapping */ 00085 struct net_device *netdev; 00086 void __iomem *iobase; /* address of the device */ 00087 struct mutex lock; /* dev-level lock */ 00088 00089 struct ieee80211_low_level_stats ll_stats; 00090 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; 00091 struct ieee80211_channel channels[ATH_CHAN_MAX]; 00092 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES]; 00093 struct ath5k_hw *ah; /* Atheros HW */ 00094 00095 struct ieee80211_supported_band *curband; 00096 00097 unsigned int debug_level; /* debug info */ 00098 00099 struct ath5k_buf *bufptr; /* allocated buffer ptr */ 00100 struct ath5k_desc *desc; /* TX/RX descriptors */ 00101 dma_addr_t desc_daddr; /* DMA (physical) address */ 00102 size_t desc_len; /* size of TX/RX descriptors */ 00103 u16 cachelsz; /* cache line size */ 00104 00105 DECLARE_BITMAP(status, 5); 00106 #define ATH_STAT_INVALID 0 /* disable hardware accesses */ 00107 #define ATH_STAT_MRRETRY 1 /* multi-rate retry support */ 00108 #define ATH_STAT_PROMISC 2 00109 #define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */ 00110 #define ATH_STAT_STARTED 4 /* opened & irqs enabled */ 00111 00112 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */ 00113 struct ieee80211_channel *curchan; /* current h/w channel */ 00114 00115 enum ath5k_int imask; /* interrupt mask copy */ 00116 00117 unsigned char bssidmask[ETH_ALEN]; 00118 00119 struct tasklet_struct restq; /* reset tasklet */ 00120 00121 unsigned int rxbufsize; /* rx size based on mtu */ 00122 struct list_head rxbuf; /* receive buffer */ 00123 spinlock_t rxbuflock; 00124 u32 *rxlink; /* link ptr in last RX desc */ 00125 00126 struct list_head txbuf; /* transmit buffer */ 00127 spinlock_t txbuflock; 00128 unsigned int txbuf_len; /* buf count in txbuf list */ 00129 struct ath5k_txq txqs[1]; /* beacon and tx */ 00130 00131 // struct tasklet_struct calib; /* calibration tasklet */ 00132 00133 struct ath5k_txq *txq; /* beacon and tx*/ 00134 struct ieee80211_tx_info tx_info; 00135 00136 int power_level; /* Requested tx power in dbm */ 00137 bool assoc; /* assocate state */ 00138 }; 00139 00140 #define ath5k_hw_hasbssidmask(_ah) \ 00141 (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0) 00142 #define ath5k_hw_hasveol(_ah) \ 00143 (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0) 00144 00145 #endif