00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023 #include <linux/pci.h>
00024 #include "ath5k.h"
00025 #include "reg.h"
00026 #include "debug.h"
00027 #include "base.h"
00028
00034 static int ath5k_hw_post(struct ath5k_hw *ah)
00035 {
00036
00037 static const u32 static_pattern[4] = {
00038 0x55555555, 0xaaaaaaaa,
00039 0x66666666, 0x99999999
00040 };
00041 static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
00042 int i, c;
00043 u16 cur_reg;
00044 u32 var_pattern;
00045 u32 init_val;
00046 u32 cur_val;
00047
00048 for (c = 0; c < 2; c++) {
00049
00050 cur_reg = regs[c];
00051
00052
00053 init_val = ath5k_hw_reg_read(ah, cur_reg);
00054
00055 for (i = 0; i < 256; i++) {
00056 var_pattern = i << 16 | i;
00057 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
00058 cur_val = ath5k_hw_reg_read(ah, cur_reg);
00059
00060 if (cur_val != var_pattern) {
00061 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
00062 return -EAGAIN;
00063 }
00064
00065
00066 var_pattern = 0x0039080f;
00067 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
00068 }
00069
00070 for (i = 0; i < 4; i++) {
00071 var_pattern = static_pattern[i];
00072 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
00073 cur_val = ath5k_hw_reg_read(ah, cur_reg);
00074
00075 if (cur_val != var_pattern) {
00076 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
00077 return -EAGAIN;
00078 }
00079
00080
00081 var_pattern = 0x003b080f;
00082 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
00083 }
00084
00085
00086 ath5k_hw_reg_write(ah, init_val, cur_reg);
00087
00088 }
00089
00090 return 0;
00091
00092 }
00093
00104 int ath5k_hw_attach(struct ath5k_softc *sc)
00105 {
00106 struct ath5k_hw *ah = sc->ah;
00107 struct pci_dev *pdev = sc->pdev;
00108 struct ath5k_eeprom_info *ee;
00109 int ret;
00110 u32 srev;
00111 u8 mac[ETH_ALEN];
00112
00113
00114
00115
00116 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
00117 ah->ah_turbo = false;
00118 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
00119 ah->ah_imr = 0;
00120 ah->ah_atim_window = 0;
00121 ah->ah_aifs = AR5K_TUNE_AIFS;
00122 ah->ah_cw_min = AR5K_TUNE_CWMIN;
00123 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
00124 ah->ah_software_retry = false;
00125
00126
00127
00128
00129 srev = ath5k_hw_reg_read(ah, AR5K_SREV);
00130 if (srev < AR5K_SREV_AR5311)
00131 ah->ah_version = AR5K_AR5210;
00132 else if (srev < AR5K_SREV_AR5212)
00133 ah->ah_version = AR5K_AR5211;
00134 else
00135 ah->ah_version = AR5K_AR5212;
00136
00137
00138 ret = ath5k_hw_init_desc_functions(ah);
00139 if (ret)
00140 goto err_free;
00141
00142
00143 ret = ath5k_hw_nic_wakeup(ah, 0, true);
00144 if (ret)
00145 goto err_free;
00146
00147
00148 ah->ah_mac_srev = srev;
00149 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
00150 ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
00151 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
00152 0xffffffff;
00153 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
00154 CHANNEL_5GHZ);
00155 ah->ah_phy = AR5K_PHY(0);
00156
00157
00158 switch (ah->ah_radio_5ghz_revision & 0xf0) {
00159 case AR5K_SREV_RAD_5111:
00160 ah->ah_radio = AR5K_RF5111;
00161 ah->ah_single_chip = false;
00162 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
00163 CHANNEL_2GHZ);
00164 break;
00165 case AR5K_SREV_RAD_5112:
00166 case AR5K_SREV_RAD_2112:
00167 ah->ah_radio = AR5K_RF5112;
00168 ah->ah_single_chip = false;
00169 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
00170 CHANNEL_2GHZ);
00171 break;
00172 case AR5K_SREV_RAD_2413:
00173 ah->ah_radio = AR5K_RF2413;
00174 ah->ah_single_chip = true;
00175 break;
00176 case AR5K_SREV_RAD_5413:
00177 ah->ah_radio = AR5K_RF5413;
00178 ah->ah_single_chip = true;
00179 break;
00180 case AR5K_SREV_RAD_2316:
00181 ah->ah_radio = AR5K_RF2316;
00182 ah->ah_single_chip = true;
00183 break;
00184 case AR5K_SREV_RAD_2317:
00185 ah->ah_radio = AR5K_RF2317;
00186 ah->ah_single_chip = true;
00187 break;
00188 case AR5K_SREV_RAD_5424:
00189 if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
00190 ah->ah_mac_version == AR5K_SREV_AR2417){
00191 ah->ah_radio = AR5K_RF2425;
00192 ah->ah_single_chip = true;
00193 } else {
00194 ah->ah_radio = AR5K_RF5413;
00195 ah->ah_single_chip = true;
00196 }
00197 break;
00198 default:
00199
00200 if (ah->ah_version == AR5K_AR5210) {
00201 ah->ah_radio = AR5K_RF5110;
00202 ah->ah_single_chip = false;
00203 } else if (ah->ah_version == AR5K_AR5211) {
00204 ah->ah_radio = AR5K_RF5111;
00205 ah->ah_single_chip = false;
00206 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
00207 CHANNEL_2GHZ);
00208 } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
00209 ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
00210 ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
00211 ah->ah_radio = AR5K_RF2425;
00212 ah->ah_single_chip = true;
00213 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
00214 } else if (srev == AR5K_SREV_AR5213A &&
00215 ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
00216 ah->ah_radio = AR5K_RF5112;
00217 ah->ah_single_chip = false;
00218 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
00219 } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
00220 ah->ah_radio = AR5K_RF2316;
00221 ah->ah_single_chip = true;
00222 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
00223 } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
00224 ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
00225 ah->ah_radio = AR5K_RF5413;
00226 ah->ah_single_chip = true;
00227 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
00228 } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
00229 ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
00230 ah->ah_radio = AR5K_RF2413;
00231 ah->ah_single_chip = true;
00232 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
00233 } else {
00234 ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
00235 ret = -ENODEV;
00236 goto err_free;
00237 }
00238 }
00239
00240
00241
00242 if ((srev >= AR5K_SREV_AR5416) &&
00243 (srev < AR5K_SREV_AR2425)) {
00244 ATH5K_ERR(sc, "Device not yet supported.\n");
00245 ret = -ENODEV;
00246 goto err_free;
00247 }
00248
00249
00250
00251
00252 ret = ath5k_hw_post(ah);
00253 if (ret)
00254 goto err_free;
00255
00256
00257 if (srev >= AR5K_SREV_AR5213A)
00258 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
00259
00260
00261
00262
00263
00264 ret = ath5k_eeprom_init(ah);
00265 if (ret) {
00266 ATH5K_ERR(sc, "unable to init EEPROM\n");
00267 goto err_free;
00268 }
00269
00270 ee = &ah->ah_capabilities.cap_eeprom;
00271
00272
00273
00274
00275 if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
00276 ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
00277 ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
00278
00279
00280 ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
00281 ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
00282
00283
00284
00285
00286 if (ee->ee_serdes)
00287 ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
00288 else
00289 ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
00290
00291
00292 ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
00293
00294
00295 ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
00296 ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
00297 ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
00298
00299
00300 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
00301 mdelay(1);
00302 }
00303
00304
00305 ret = ath5k_hw_set_capabilities(ah);
00306 if (ret) {
00307 ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
00308 sc->pdev->device);
00309 goto err_free;
00310 }
00311
00312 if (srev >= AR5K_SREV_AR2414) {
00313 ah->ah_combined_mic = true;
00314 AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
00315 AR5K_MISC_MODE_COMBINED_MIC);
00316 }
00317
00318
00319 ret = ath5k_eeprom_read_mac(ah, mac);
00320 if (ret) {
00321 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
00322 sc->pdev->device);
00323 goto err_free;
00324 }
00325
00326 ath5k_hw_set_lladdr(ah, mac);
00327
00328
00329 memset(ah->ah_bssid, 0xff, ETH_ALEN);
00330 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
00331 ath5k_hw_set_opmode(ah);
00332
00333 ath5k_hw_rfgain_opt_init(ah);
00334
00335 return 0;
00336 err_free:
00337 kfree(ah);
00338 return ret;
00339 }
00340
00346 void ath5k_hw_detach(struct ath5k_hw *ah)
00347 {
00348 ATH5K_TRACE(ah->ah_sc);
00349
00350 __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
00351
00352 if (ah->ah_rf_banks != NULL)
00353 kfree(ah->ah_rf_banks);
00354
00355 ath5k_eeprom_detach(ah);
00356
00357
00358 }