stm32h7xx_hal_dsi.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_DSI_H
22 #define STM32H7xx_HAL_DSI_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 #if defined(DSI)
29 /* Includes ------------------------------------------------------------------*/
30 #include "stm32h7xx_hal_def.h"
31 
41 /* Exported types ------------------------------------------------------------*/
45 typedef struct
46 {
47  uint32_t AutomaticClockLaneControl;
50  uint32_t TXEscapeCkdiv;
53  uint32_t NumberOfLanes;
56 } DSI_InitTypeDef;
57 
61 typedef struct
62 {
63  uint32_t PLLNDIV;
66  uint32_t PLLIDF;
69  uint32_t PLLODF;
72 } DSI_PLLInitTypeDef;
73 
77 typedef struct
78 {
79  uint32_t VirtualChannelID;
81  uint32_t ColorCoding;
84  uint32_t LooselyPacked;
88  uint32_t Mode;
91  uint32_t PacketSize;
93  uint32_t NumberOfChunks;
95  uint32_t NullPacketSize;
97  uint32_t HSPolarity;
100  uint32_t VSPolarity;
103  uint32_t DEPolarity;
106  uint32_t HorizontalSyncActive;
108  uint32_t HorizontalBackPorch;
110  uint32_t HorizontalLine;
112  uint32_t VerticalSyncActive;
114  uint32_t VerticalBackPorch;
116  uint32_t VerticalFrontPorch;
118  uint32_t VerticalActive;
120  uint32_t LPCommandEnable;
123  uint32_t LPLargestPacketSize;
126  uint32_t LPVACTLargestPacketSize;
129  uint32_t LPHorizontalFrontPorchEnable;
132  uint32_t LPHorizontalBackPorchEnable;
135  uint32_t LPVerticalActiveEnable;
138  uint32_t LPVerticalFrontPorchEnable;
141  uint32_t LPVerticalBackPorchEnable;
144  uint32_t LPVerticalSyncActiveEnable;
147  uint32_t FrameBTAAcknowledgeEnable;
150 } DSI_VidCfgTypeDef;
151 
155 typedef struct
156 {
157  uint32_t VirtualChannelID;
159  uint32_t ColorCoding;
162  uint32_t CommandSize;
165  uint32_t TearingEffectSource;
168  uint32_t TearingEffectPolarity;
171  uint32_t HSPolarity;
174  uint32_t VSPolarity;
177  uint32_t DEPolarity;
180  uint32_t VSyncPol;
183  uint32_t AutomaticRefresh;
186  uint32_t TEAcknowledgeRequest;
189 } DSI_CmdCfgTypeDef;
190 
194 typedef struct
195 {
196  uint32_t LPGenShortWriteNoP;
199  uint32_t LPGenShortWriteOneP;
202  uint32_t LPGenShortWriteTwoP;
205  uint32_t LPGenShortReadNoP;
208  uint32_t LPGenShortReadOneP;
211  uint32_t LPGenShortReadTwoP;
214  uint32_t LPGenLongWrite;
217  uint32_t LPDcsShortWriteNoP;
220  uint32_t LPDcsShortWriteOneP;
223  uint32_t LPDcsShortReadNoP;
226  uint32_t LPDcsLongWrite;
229  uint32_t LPMaxReadPacket;
232  uint32_t AcknowledgeRequest;
235 } DSI_LPCmdTypeDef;
236 
240 typedef struct
241 {
242  uint32_t ClockLaneHS2LPTime;
245  uint32_t ClockLaneLP2HSTime;
248  uint32_t DataLaneHS2LPTime;
251  uint32_t DataLaneLP2HSTime;
254  uint32_t DataLaneMaxReadTime;
256  uint32_t StopWaitTime;
259 } DSI_PHY_TimerTypeDef;
260 
264 typedef struct
265 {
266  uint32_t TimeoutCkdiv;
268  uint32_t HighSpeedTransmissionTimeout;
270  uint32_t LowPowerReceptionTimeout;
272  uint32_t HighSpeedReadTimeout;
274  uint32_t LowPowerReadTimeout;
276  uint32_t HighSpeedWriteTimeout;
278  uint32_t HighSpeedWritePrespMode;
281  uint32_t LowPowerWriteTimeout;
283  uint32_t BTATimeout;
285 } DSI_HOST_TimeoutTypeDef;
286 
290 typedef enum
291 {
292  HAL_DSI_STATE_RESET = 0x00U,
293  HAL_DSI_STATE_READY = 0x01U,
294  HAL_DSI_STATE_ERROR = 0x02U,
295  HAL_DSI_STATE_BUSY = 0x03U,
296  HAL_DSI_STATE_TIMEOUT = 0x04U
297 } HAL_DSI_StateTypeDef;
298 
302 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
303 typedef struct __DSI_HandleTypeDef
304 #else
305 typedef struct
306 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
307 {
308  DSI_TypeDef *Instance;
309  DSI_InitTypeDef Init;
310  HAL_LockTypeDef Lock;
311  __IO HAL_DSI_StateTypeDef State;
312  __IO uint32_t ErrorCode;
313  uint32_t ErrorMsk;
315 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
316  void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi);
317  void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi);
318  void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi);
320  void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi);
321  void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi);
323 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
324 
325 } DSI_HandleTypeDef;
326 
327 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
328 
331 typedef enum
332 {
333  HAL_DSI_MSPINIT_CB_ID = 0x00U,
334  HAL_DSI_MSPDEINIT_CB_ID = 0x01U,
336  HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U,
337  HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U,
338  HAL_DSI_ERROR_CB_ID = 0x04U
340 } HAL_DSI_CallbackIDTypeDef;
341 
345 typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);
347 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
348 
349 /* Exported constants --------------------------------------------------------*/
356 #define DSI_ENTER_IDLE_MODE 0x39U
357 #define DSI_ENTER_INVERT_MODE 0x21U
358 #define DSI_ENTER_NORMAL_MODE 0x13U
359 #define DSI_ENTER_PARTIAL_MODE 0x12U
360 #define DSI_ENTER_SLEEP_MODE 0x10U
361 #define DSI_EXIT_IDLE_MODE 0x38U
362 #define DSI_EXIT_INVERT_MODE 0x20U
363 #define DSI_EXIT_SLEEP_MODE 0x11U
364 #define DSI_GET_3D_CONTROL 0x3FU
365 #define DSI_GET_ADDRESS_MODE 0x0BU
366 #define DSI_GET_BLUE_CHANNEL 0x08U
367 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
368 #define DSI_GET_DISPLAY_MODE 0x0DU
369 #define DSI_GET_GREEN_CHANNEL 0x07U
370 #define DSI_GET_PIXEL_FORMAT 0x0CU
371 #define DSI_GET_POWER_MODE 0x0AU
372 #define DSI_GET_RED_CHANNEL 0x06U
373 #define DSI_GET_SCANLINE 0x45U
374 #define DSI_GET_SIGNAL_MODE 0x0EU
375 #define DSI_NOP 0x00U
376 #define DSI_READ_DDB_CONTINUE 0xA8U
377 #define DSI_READ_DDB_START 0xA1U
378 #define DSI_READ_MEMORY_CONTINUE 0x3EU
379 #define DSI_READ_MEMORY_START 0x2EU
380 #define DSI_SET_3D_CONTROL 0x3DU
381 #define DSI_SET_ADDRESS_MODE 0x36U
382 #define DSI_SET_COLUMN_ADDRESS 0x2AU
383 #define DSI_SET_DISPLAY_OFF 0x28U
384 #define DSI_SET_DISPLAY_ON 0x29U
385 #define DSI_SET_GAMMA_CURVE 0x26U
386 #define DSI_SET_PAGE_ADDRESS 0x2BU
387 #define DSI_SET_PARTIAL_COLUMNS 0x31U
388 #define DSI_SET_PARTIAL_ROWS 0x30U
389 #define DSI_SET_PIXEL_FORMAT 0x3AU
390 #define DSI_SET_SCROLL_AREA 0x33U
391 #define DSI_SET_SCROLL_START 0x37U
392 #define DSI_SET_TEAR_OFF 0x34U
393 #define DSI_SET_TEAR_ON 0x35U
394 #define DSI_SET_TEAR_SCANLINE 0x44U
395 #define DSI_SET_VSYNC_TIMING 0x40U
396 #define DSI_SOFT_RESET 0x01U
397 #define DSI_WRITE_LUT 0x2DU
398 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU
399 #define DSI_WRITE_MEMORY_START 0x2CU
400 
407 #define DSI_VID_MODE_NB_PULSES 0U
408 #define DSI_VID_MODE_NB_EVENTS 1U
409 #define DSI_VID_MODE_BURST 2U
410 
417 #define DSI_COLOR_MODE_FULL 0x00000000U
418 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
419 
426 #define DSI_DISPLAY_ON 0x00000000U
427 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN
428 
435 #define DSI_LP_COMMAND_DISABLE 0x00000000U
436 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
437 
444 #define DSI_LP_HFP_DISABLE 0x00000000U
445 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
446 
453 #define DSI_LP_HBP_DISABLE 0x00000000U
454 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
455 
462 #define DSI_LP_VACT_DISABLE 0x00000000U
463 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
464 
471 #define DSI_LP_VFP_DISABLE 0x00000000U
472 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
473 
480 #define DSI_LP_VBP_DISABLE 0x00000000U
481 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
482 
489 #define DSI_LP_VSYNC_DISABLE 0x00000000U
490 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
491 
498 #define DSI_FBTAA_DISABLE 0x00000000U
499 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
500 
507 #define DSI_TE_DSILINK 0x00000000U
508 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
509 
516 #define DSI_TE_RISING_EDGE 0x00000000U
517 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
518 
525 #define DSI_VSYNC_FALLING 0x00000000U
526 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
527 
534 #define DSI_AR_DISABLE 0x00000000U
535 #define DSI_AR_ENABLE DSI_WCFGR_AR
536 
543 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
544 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
545 
552 #define DSI_ACKNOWLEDGE_DISABLE 0x00000000U
553 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
554 
561 #define DSI_LP_GSW0P_DISABLE 0x00000000U
562 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
563 
570 #define DSI_LP_GSW1P_DISABLE 0x00000000U
571 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
572 
579 #define DSI_LP_GSW2P_DISABLE 0x00000000U
580 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
581 
588 #define DSI_LP_GSR0P_DISABLE 0x00000000U
589 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
590 
597 #define DSI_LP_GSR1P_DISABLE 0x00000000U
598 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
599 
606 #define DSI_LP_GSR2P_DISABLE 0x00000000U
607 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
608 
615 #define DSI_LP_GLW_DISABLE 0x00000000U
616 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
617 
624 #define DSI_LP_DSW0P_DISABLE 0x00000000U
625 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
626 
633 #define DSI_LP_DSW1P_DISABLE 0x00000000U
634 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
635 
642 #define DSI_LP_DSR0P_DISABLE 0x00000000U
643 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
644 
651 #define DSI_LP_DLW_DISABLE 0x00000000U
652 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
653 
660 #define DSI_LP_MRDP_DISABLE 0x00000000U
661 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
662 
669 #define DSI_HS_PM_DISABLE 0x00000000U
670 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM
671 
679 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
680 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
681 
688 #define DSI_ONE_DATA_LANE 0U
689 #define DSI_TWO_DATA_LANES 1U
690 
697 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
698 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
699 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
700 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
701 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
702 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
703  DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
704  DSI_FLOW_CONTROL_EOTP_TX)
705 
712 #define DSI_RGB565 0x00000000U
713 #define DSI_RGB666 0x00000003U
714 #define DSI_RGB888 0x00000005U
715 
722 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
723 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
724 
731 #define DSI_HSYNC_ACTIVE_HIGH 0x00000000U
732 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
733 
740 #define DSI_VSYNC_ACTIVE_HIGH 0x00000000U
741 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
742 
749 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
750 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
751 
758 #define DSI_PLL_IN_DIV1 0x00000001U
759 #define DSI_PLL_IN_DIV2 0x00000002U
760 #define DSI_PLL_IN_DIV3 0x00000003U
761 #define DSI_PLL_IN_DIV4 0x00000004U
762 #define DSI_PLL_IN_DIV5 0x00000005U
763 #define DSI_PLL_IN_DIV6 0x00000006U
764 #define DSI_PLL_IN_DIV7 0x00000007U
765 
772 #define DSI_PLL_OUT_DIV1 0x00000000U
773 #define DSI_PLL_OUT_DIV2 0x00000001U
774 #define DSI_PLL_OUT_DIV4 0x00000002U
775 #define DSI_PLL_OUT_DIV8 0x00000003U
776 
783 #define DSI_FLAG_TE DSI_WISR_TEIF
784 #define DSI_FLAG_ER DSI_WISR_ERIF
785 #define DSI_FLAG_BUSY DSI_WISR_BUSY
786 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS
787 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF
788 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF
789 #define DSI_FLAG_RRS DSI_WISR_RRS
790 #define DSI_FLAG_RR DSI_WISR_RRIF
791 
798 #define DSI_IT_TE DSI_WIER_TEIE
799 #define DSI_IT_ER DSI_WIER_ERIE
800 #define DSI_IT_PLLL DSI_WIER_PLLLIE
801 #define DSI_IT_PLLU DSI_WIER_PLLUIE
802 #define DSI_IT_RR DSI_WIER_RRIE
803 
810 #define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U
811 #define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U
812 #define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U
813 #define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U
814 #define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U
822 #define DSI_DCS_LONG_PKT_WRITE 0x00000039U
823 #define DSI_GEN_LONG_PKT_WRITE 0x00000029U
831 #define DSI_DCS_SHORT_PKT_READ 0x00000006U
832 #define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U
833 #define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U
834 #define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U
842 #define HAL_DSI_ERROR_NONE 0U
843 #define HAL_DSI_ERROR_ACK 0x00000001U
844 #define HAL_DSI_ERROR_PHY 0x00000002U
845 #define HAL_DSI_ERROR_TX 0x00000004U
846 #define HAL_DSI_ERROR_RX 0x00000008U
847 #define HAL_DSI_ERROR_ECC 0x00000010U
848 #define HAL_DSI_ERROR_CRC 0x00000020U
849 #define HAL_DSI_ERROR_PSE 0x00000040U
850 #define HAL_DSI_ERROR_EOT 0x00000080U
851 #define HAL_DSI_ERROR_OVF 0x00000100U
852 #define HAL_DSI_ERROR_GEN 0x00000200U
853 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
854 #define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U
855 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
856 
863 #define DSI_CLOCK_LANE 0x00000000U
864 #define DSI_DATA_LANES 0x00000001U
865 
872 #define DSI_SLEW_RATE_HSTX 0x00000000U
873 #define DSI_SLEW_RATE_LPTX 0x00000001U
874 #define DSI_HS_DELAY 0x00000002U
875 
882 #define DSI_SWAP_LANE_PINS 0x00000000U
883 #define DSI_INVERT_HS_SIGNAL 0x00000001U
884 
891 #define DSI_CLK_LANE 0x00000000U
892 #define DSI_DATA_LANE0 0x00000001U
893 #define DSI_DATA_LANE1 0x00000002U
894 
901 #define DSI_TCLK_POST 0x00000000U
902 #define DSI_TLPX_CLK 0x00000001U
903 #define DSI_THS_EXIT 0x00000002U
904 #define DSI_TLPX_DATA 0x00000003U
905 #define DSI_THS_ZERO 0x00000004U
906 #define DSI_THS_TRAIL 0x00000005U
907 #define DSI_THS_PREPARE 0x00000006U
908 #define DSI_TCLK_ZERO 0x00000007U
909 #define DSI_TCLK_PREPARE 0x00000008U
910 
918 /* Exported macros -----------------------------------------------------------*/
928 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
929 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \
930  (__HANDLE__)->State = HAL_DSI_STATE_RESET; \
931  (__HANDLE__)->MspInitCallback = NULL; \
932  (__HANDLE__)->MspDeInitCallback = NULL; \
933  } while(0)
934 #else
935 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)
936 #endif /*USE_HAL_DSI_REGISTER_CALLBACKS */
937 
943 #define __HAL_DSI_ENABLE(__HANDLE__) do { \
944  __IO uint32_t tmpreg = 0x00U; \
945  SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
946  /* Delay after an DSI Host enabling */ \
947  tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
948  UNUSED(tmpreg); \
949  } while(0U)
950 
956 #define __HAL_DSI_DISABLE(__HANDLE__) do { \
957  __IO uint32_t tmpreg = 0x00U; \
958  CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
959  /* Delay after an DSI Host disabling */ \
960  tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
961  UNUSED(tmpreg); \
962  } while(0U)
963 
969 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
970  __IO uint32_t tmpreg = 0x00U; \
971  SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
972  /* Delay after an DSI warpper enabling */ \
973  tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
974  UNUSED(tmpreg); \
975  } while(0U)
976 
982 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
983  __IO uint32_t tmpreg = 0x00U; \
984  CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
985  /* Delay after an DSI warpper disabling*/ \
986  tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
987  UNUSED(tmpreg); \
988  } while(0U)
989 
995 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
996  __IO uint32_t tmpreg = 0x00U; \
997  SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
998  /* Delay after an DSI PLL enabling */ \
999  tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1000  UNUSED(tmpreg); \
1001  } while(0U)
1002 
1008 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
1009  __IO uint32_t tmpreg = 0x00U; \
1010  CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1011  /* Delay after an DSI PLL disabling */ \
1012  tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
1013  UNUSED(tmpreg); \
1014  } while(0U)
1015 
1021 #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
1022  __IO uint32_t tmpreg = 0x00U; \
1023  SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1024  /* Delay after an DSI regulator enabling */ \
1025  tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1026  UNUSED(tmpreg); \
1027  } while(0U)
1028 
1034 #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
1035  __IO uint32_t tmpreg = 0x00U; \
1036  CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1037  /* Delay after an DSI regulator disabling */ \
1038  tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
1039  UNUSED(tmpreg); \
1040  } while(0U)
1041 
1057 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
1058 
1071 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
1072 
1085 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))
1086 
1099 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
1100 
1113 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
1114 
1119 /* Exported functions --------------------------------------------------------*/
1123 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
1124 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
1125 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
1126 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
1127 
1128 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
1129 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
1130 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
1131 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
1132 
1133 /* Callbacks Register/UnRegister functions ***********************************/
1134 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
1135 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
1136  pDSI_CallbackTypeDef pCallback);
1137 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
1138 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
1139 
1140 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
1141 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
1142 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
1143 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);
1144 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
1145 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);
1146 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);
1147 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
1148 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
1149 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
1150 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
1151 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
1152 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1153  uint32_t ChannelID,
1154  uint32_t Mode,
1155  uint32_t Param1,
1156  uint32_t Param2);
1157 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1158  uint32_t ChannelID,
1159  uint32_t Mode,
1160  uint32_t NbParams,
1161  uint32_t Param1,
1162  uint8_t *ParametersTable);
1163 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1164  uint32_t ChannelNbr,
1165  uint8_t *Array,
1166  uint32_t Size,
1167  uint32_t Mode,
1168  uint32_t DCSCmd,
1169  uint8_t *ParametersTable);
1170 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
1171 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
1172 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
1173 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
1174 
1175 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
1176 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
1177 
1178 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,
1179  uint32_t Value);
1180 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
1181 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
1182 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,
1183  FunctionalState State);
1184 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State,
1185  uint32_t Value);
1186 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
1187 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
1188 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
1189 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
1190 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
1191 
1192 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
1193 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
1194 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
1199 /* Private types -------------------------------------------------------------*/
1208 /* Private defines -----------------------------------------------------------*/
1217 /* Private variables ---------------------------------------------------------*/
1226 /* Private constants ---------------------------------------------------------*/
1230 #define DSI_MAX_RETURN_PKT_SIZE (0x00000037U)
1235 /* Private macros ------------------------------------------------------------*/
1236 
1239 #define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
1240 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \
1241  ((IDF) == DSI_PLL_IN_DIV2) || \
1242  ((IDF) == DSI_PLL_IN_DIV3) || \
1243  ((IDF) == DSI_PLL_IN_DIV4) || \
1244  ((IDF) == DSI_PLL_IN_DIV5) || \
1245  ((IDF) == DSI_PLL_IN_DIV6) || \
1246  ((IDF) == DSI_PLL_IN_DIV7))
1247 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \
1248  ((ODF) == DSI_PLL_OUT_DIV2) || \
1249  ((ODF) == DSI_PLL_OUT_DIV4) || \
1250  ((ODF) == DSI_PLL_OUT_DIV8))
1251 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
1252 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
1253 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
1254 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
1255 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
1256 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
1257 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
1258 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
1259 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
1260  ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
1261  ((VideoModeType) == DSI_VID_MODE_BURST))
1262 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
1263 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
1264 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
1265 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
1266 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
1267 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
1268 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
1269 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
1270 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
1271 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
1272 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
1273 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
1274 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
1275 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
1276 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
1277 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
1278 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
1279 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
1280 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
1281 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
1282 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
1283 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
1284 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
1285 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
1286 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
1287 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
1288 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
1289 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
1290 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
1291  ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
1292  ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
1293  ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \
1294  ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
1295 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \
1296  ((MODE) == DSI_GEN_LONG_PKT_WRITE))
1297 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \
1298  ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
1299  ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
1300  ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
1301 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
1302 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
1303 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
1304 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
1305 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \
1306  ((Timing) == DSI_TLPX_CLK ) || \
1307  ((Timing) == DSI_THS_EXIT ) || \
1308  ((Timing) == DSI_TLPX_DATA ) || \
1309  ((Timing) == DSI_THS_ZERO ) || \
1310  ((Timing) == DSI_THS_TRAIL ) || \
1311  ((Timing) == DSI_THS_PREPARE ) || \
1312  ((Timing) == DSI_TCLK_ZERO ) || \
1313  ((Timing) == DSI_TCLK_PREPARE))
1314 
1319 /* Private functions prototypes ----------------------------------------------*/
1328 /* Private functions ---------------------------------------------------------*/
1344 #endif /* DSI */
1345 
1346 #ifdef __cplusplus
1347 }
1348 #endif
1349 
1350 #endif /* STM32H7xx_HAL_DSI_H */
1351 
1352 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
Init
napi_value Init(napi_env env, napi_value exports)
Definition: porcupine/demo/c/pvrecorder/node/pv_recorder_napi.c:197
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
Timing
static FMC_SDRAM_TimingTypeDef Timing
Definition: stm32f769i_discovery_sdram.c:124
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:51
DSI_TypeDef
DSI Controller.
Definition: stm32f469xx.h:408
Mode
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/stb_vorbis.c:745
FunctionalState
FunctionalState
Definition: stm32f407/stm32f407g-disc1/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:191

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:14:54