stm32f4xx_hal_eth.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F4xx_HAL_ETH_H
22 #define __STM32F4xx_HAL_ETH_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
29  defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
30 /* Includes ------------------------------------------------------------------*/
31 #include "stm32f4xx_hal_def.h"
32 
44 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
45 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
46  ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
47 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
48  ((SPEED) == ETH_SPEED_100M))
49 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
50  ((MODE) == ETH_MODE_HALFDUPLEX))
51 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
52  ((MODE) == ETH_RXINTERRUPT_MODE))
53 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
54  ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
55 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
56  ((MODE) == ETH_MEDIA_INTERFACE_RMII))
57 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
58  ((CMD) == ETH_WATCHDOG_DISABLE))
59 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
60  ((CMD) == ETH_JABBER_DISABLE))
61 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
62  ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
63  ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
64  ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
65  ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
66  ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
67  ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
68  ((GAP) == ETH_INTERFRAMEGAP_40BIT))
69 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
70  ((CMD) == ETH_CARRIERSENCE_DISABLE))
71 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
72  ((CMD) == ETH_RECEIVEOWN_DISABLE))
73 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
74  ((CMD) == ETH_LOOPBACKMODE_DISABLE))
75 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
76  ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
77 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
78  ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
79 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
80  ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
81 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
82  ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
83  ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
84  ((LIMIT) == ETH_BACKOFFLIMIT_1))
85 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
86  ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
87 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
88  ((CMD) == ETH_RECEIVEAll_DISABLE))
89 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
90  ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
91  ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
92 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
93  ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
94  ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
95 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
96  ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
97 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
98  ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
99 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
100  ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
101 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
102  ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
103  ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
104  ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
105 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
106  ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
107  ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
108 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
109 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
110  ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
111 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
112  ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
113  ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
114  ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
115 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
116  ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
117 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
118  ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
119 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
120  ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
121 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
122  ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
123 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
124 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
125  ((ADDRESS) == ETH_MAC_ADDRESS1) || \
126  ((ADDRESS) == ETH_MAC_ADDRESS2) || \
127  ((ADDRESS) == ETH_MAC_ADDRESS3))
128 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
129  ((ADDRESS) == ETH_MAC_ADDRESS2) || \
130  ((ADDRESS) == ETH_MAC_ADDRESS3))
131 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
132  ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
133 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
134  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
135  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
136  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
137  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
138  ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
139 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
140  ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
141 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
142  ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
143 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
144  ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
145 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
146  ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
147 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
148  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
149  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
150  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
151  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
152  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
153  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
154  ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
155 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
156  ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
157 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
158  ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
159 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
160  ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
161  ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
162  ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
163 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
164  ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
165 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
166  ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
167 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
168  ((CMD) == ETH_FIXEDBURST_DISABLE))
169 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
170  ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
171  ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
172  ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
173  ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
174  ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
175  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
176  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
177  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
178  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
179  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
180  ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
181 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
182  ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
183  ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
184  ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
185  ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
186  ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
187  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
188  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
189  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
190  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
191  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
192  ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
193 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
194 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
195  ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
196  ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
197  ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
198  ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
199 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
200  ((FLAG) == ETH_DMATXDESC_IC) || \
201  ((FLAG) == ETH_DMATXDESC_LS) || \
202  ((FLAG) == ETH_DMATXDESC_FS) || \
203  ((FLAG) == ETH_DMATXDESC_DC) || \
204  ((FLAG) == ETH_DMATXDESC_DP) || \
205  ((FLAG) == ETH_DMATXDESC_TTSE) || \
206  ((FLAG) == ETH_DMATXDESC_TER) || \
207  ((FLAG) == ETH_DMATXDESC_TCH) || \
208  ((FLAG) == ETH_DMATXDESC_TTSS) || \
209  ((FLAG) == ETH_DMATXDESC_IHE) || \
210  ((FLAG) == ETH_DMATXDESC_ES) || \
211  ((FLAG) == ETH_DMATXDESC_JT) || \
212  ((FLAG) == ETH_DMATXDESC_FF) || \
213  ((FLAG) == ETH_DMATXDESC_PCE) || \
214  ((FLAG) == ETH_DMATXDESC_LCA) || \
215  ((FLAG) == ETH_DMATXDESC_NC) || \
216  ((FLAG) == ETH_DMATXDESC_LCO) || \
217  ((FLAG) == ETH_DMATXDESC_EC) || \
218  ((FLAG) == ETH_DMATXDESC_VF) || \
219  ((FLAG) == ETH_DMATXDESC_CC) || \
220  ((FLAG) == ETH_DMATXDESC_ED) || \
221  ((FLAG) == ETH_DMATXDESC_UF) || \
222  ((FLAG) == ETH_DMATXDESC_DB))
223 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
224  ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
225 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
226  ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
227  ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
228  ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
229 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
230 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
231  ((FLAG) == ETH_DMARXDESC_AFM) || \
232  ((FLAG) == ETH_DMARXDESC_ES) || \
233  ((FLAG) == ETH_DMARXDESC_DE) || \
234  ((FLAG) == ETH_DMARXDESC_SAF) || \
235  ((FLAG) == ETH_DMARXDESC_LE) || \
236  ((FLAG) == ETH_DMARXDESC_OE) || \
237  ((FLAG) == ETH_DMARXDESC_VLAN) || \
238  ((FLAG) == ETH_DMARXDESC_FS) || \
239  ((FLAG) == ETH_DMARXDESC_LS) || \
240  ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
241  ((FLAG) == ETH_DMARXDESC_LC) || \
242  ((FLAG) == ETH_DMARXDESC_FT) || \
243  ((FLAG) == ETH_DMARXDESC_RWT) || \
244  ((FLAG) == ETH_DMARXDESC_RE) || \
245  ((FLAG) == ETH_DMARXDESC_DBE) || \
246  ((FLAG) == ETH_DMARXDESC_CE) || \
247  ((FLAG) == ETH_DMARXDESC_MAMPCE))
248 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
249  ((BUFFER) == ETH_DMARXDESC_BUFFER2))
250 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
251  ((FLAG) == ETH_PMT_FLAG_MPR))
252 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
253 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
254  ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
255  ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
256  ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
257  ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
258  ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
259  ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
260  ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
261  ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
262  ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
263  ((FLAG) == ETH_DMA_FLAG_T))
264 #define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
265 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
266  ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
267  ((IT) == ETH_MAC_IT_PMT))
268 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
269  ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
270  ((FLAG) == ETH_MAC_FLAG_PMT))
271 #define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
272 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
273  ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
274  ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
275  ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
276  ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
277  ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
278  ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
279  ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
280  ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
281 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
282  ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
283 #define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
284  ((IT) != 0x00U))
285 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
286  ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
287  ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
288 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
289  ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
290 
298 /* Delay to wait when writing to some Ethernet registers */
299 #define ETH_REG_WRITE_DELAY 0x00000001U
300 
301 /* ETHERNET Errors */
302 #define ETH_SUCCESS 0U
303 #define ETH_ERROR 1U
304 
305 /* ETHERNET DMA Tx descriptors Collision Count Shift */
306 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
307 
308 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
309 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
310 
311 /* ETHERNET DMA Rx descriptors Frame Length Shift */
312 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
313 
314 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
315 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
316 
317 /* ETHERNET DMA Rx descriptors Frame length Shift */
318 #define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
319 
320 /* ETHERNET MAC address offsets */
321 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
322 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
323 
324 /* ETHERNET MACMIIAR register Mask */
325 #define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
326 
327 /* ETHERNET MACCR register Mask */
328 #define ETH_MACCR_CLEAR_MASK 0xFF20810FU
329 
330 /* ETHERNET MACFCR register Mask */
331 #define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
332 
333 /* ETHERNET DMAOMR register Mask */
334 #define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
335 
336 /* ETHERNET Remote Wake-up frame register length */
337 #define ETH_WAKEUP_REGISTER_LENGTH 8U
338 
339 /* ETHERNET Missed frames counter Shift */
340 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
341 
345 /* Exported types ------------------------------------------------------------*/
353 typedef enum
354 {
355  HAL_ETH_STATE_RESET = 0x00U,
356  HAL_ETH_STATE_READY = 0x01U,
357  HAL_ETH_STATE_BUSY = 0x02U,
358  HAL_ETH_STATE_BUSY_TX = 0x12U,
359  HAL_ETH_STATE_BUSY_RX = 0x22U,
360  HAL_ETH_STATE_BUSY_TX_RX = 0x32U,
361  HAL_ETH_STATE_BUSY_WR = 0x42U,
362  HAL_ETH_STATE_BUSY_RD = 0x82U,
363  HAL_ETH_STATE_TIMEOUT = 0x03U,
364  HAL_ETH_STATE_ERROR = 0x04U
365 }HAL_ETH_StateTypeDef;
366 
371 typedef struct
372 {
373  uint32_t AutoNegotiation;
378  uint32_t Speed;
381  uint32_t DuplexMode;
384  uint16_t PhyAddress;
387  uint8_t *MACAddr;
389  uint32_t RxMode;
392  uint32_t ChecksumMode;
395  uint32_t MediaInterface;
398 } ETH_InitTypeDef;
399 
400 
405 typedef struct
406 {
407  uint32_t Watchdog;
412  uint32_t Jabber;
417  uint32_t InterFrameGap;
420  uint32_t CarrierSense;
423  uint32_t ReceiveOwn;
428  uint32_t LoopbackMode;
431  uint32_t ChecksumOffload;
434  uint32_t RetryTransmission;
438  uint32_t AutomaticPadCRCStrip;
441  uint32_t BackOffLimit;
444  uint32_t DeferralCheck;
447  uint32_t ReceiveAll;
450  uint32_t SourceAddrFilter;
453  uint32_t PassControlFrames;
456  uint32_t BroadcastFramesReception;
459  uint32_t DestinationAddrFilter;
462  uint32_t PromiscuousMode;
465  uint32_t MulticastFramesFilter;
468  uint32_t UnicastFramesFilter;
471  uint32_t HashTableHigh;
474  uint32_t HashTableLow;
477  uint32_t PauseTime;
480  uint32_t ZeroQuantaPause;
483  uint32_t PauseLowThreshold;
487  uint32_t UnicastPauseFrameDetect;
491  uint32_t ReceiveFlowControl;
495  uint32_t TransmitFlowControl;
499  uint32_t VLANTagComparison;
503  uint32_t VLANTagIdentifier;
505 } ETH_MACInitTypeDef;
506 
511 typedef struct
512 {
513  uint32_t DropTCPIPChecksumErrorFrame;
516  uint32_t ReceiveStoreForward;
519  uint32_t FlushReceivedFrame;
522  uint32_t TransmitStoreForward;
525  uint32_t TransmitThresholdControl;
528  uint32_t ForwardErrorFrames;
531  uint32_t ForwardUndersizedGoodFrames;
535  uint32_t ReceiveThresholdControl;
538  uint32_t SecondFrameOperate;
542  uint32_t AddressAlignedBeats;
545  uint32_t FixedBurst;
548  uint32_t RxDMABurstLength;
551  uint32_t TxDMABurstLength;
554  uint32_t EnhancedDescriptorFormat;
557  uint32_t DescriptorSkipLength;
560  uint32_t DMAArbitration;
562 } ETH_DMAInitTypeDef;
563 
564 
569 typedef struct
570 {
571  __IO uint32_t Status;
573  uint32_t ControlBufferSize;
575  uint32_t Buffer1Addr;
577  uint32_t Buffer2NextDescAddr;
580  uint32_t ExtendedStatus;
582  uint32_t Reserved1;
584  uint32_t TimeStampLow;
586  uint32_t TimeStampHigh;
588 } ETH_DMADescTypeDef;
589 
593 typedef struct
594 {
595  ETH_DMADescTypeDef *FSRxDesc;
597  ETH_DMADescTypeDef *LSRxDesc;
599  uint32_t SegCount;
601  uint32_t length;
603  uint32_t buffer;
605 } ETH_DMARxFrameInfos;
606 
611 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
612 typedef struct __ETH_HandleTypeDef
613 #else
614 typedef struct
615 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
616 {
617  ETH_TypeDef *Instance;
619  ETH_InitTypeDef Init;
621  uint32_t LinkStatus;
623  ETH_DMADescTypeDef *RxDesc;
625  ETH_DMADescTypeDef *TxDesc;
627  ETH_DMARxFrameInfos RxFrameInfos;
629  __IO HAL_ETH_StateTypeDef State;
631  HAL_LockTypeDef Lock;
633 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
634 
635  void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth);
636  void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth);
637  void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth);
638  void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth);
639  void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth);
641 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
642 
643 } ETH_HandleTypeDef;
644 
645 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
646 
649 typedef enum
650 {
651  HAL_ETH_MSPINIT_CB_ID = 0x00U,
652  HAL_ETH_MSPDEINIT_CB_ID = 0x01U,
653  HAL_ETH_TX_COMPLETE_CB_ID = 0x02U,
654  HAL_ETH_RX_COMPLETE_CB_ID = 0x03U,
655  HAL_ETH_DMA_ERROR_CB_ID = 0x04U,
657 }HAL_ETH_CallbackIDTypeDef;
658 
662 typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth);
664 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
665 
670 /* Exported constants --------------------------------------------------------*/
678 #define ETH_MAX_PACKET_SIZE 1524U
679 #define ETH_HEADER 14U
680 #define ETH_CRC 4U
681 #define ETH_EXTRA 2U
682 #define ETH_VLAN_TAG 4U
683 #define ETH_MIN_ETH_PAYLOAD 46U
684 #define ETH_MAX_ETH_PAYLOAD 1500U
685 #define ETH_JUMBO_FRAME_PAYLOAD 9000U
687  /* Ethernet driver receive buffers are organized in a chained linked-list, when
688  an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
689  to the driver receive buffers memory.
690 
691  Depending on the size of the received ethernet packet and the size of
692  each ethernet driver receive buffer, the received packet can take one or more
693  ethernet driver receive buffer.
694 
695  In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
696  and the total count of the driver receive buffers ETH_RXBUFNB.
697 
698  The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
699  example, they can be reconfigured in the application layer to fit the application
700  needs */
701 
702 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
703  packet */
704 #ifndef ETH_RX_BUF_SIZE
705  #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
706 #endif
707 
708 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
709 #ifndef ETH_RXBUFNB
710  #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
711 #endif
712 
713 
714  /* Ethernet driver transmit buffers are organized in a chained linked-list, when
715  an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
716  driver transmit buffers memory to the TxFIFO.
717 
718  Depending on the size of the Ethernet packet to be transmitted and the size of
719  each ethernet driver transmit buffer, the packet to be transmitted can take
720  one or more ethernet driver transmit buffer.
721 
722  In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
723  and the total count of the driver transmit buffers ETH_TXBUFNB.
724 
725  The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
726  example, they can be reconfigured in the application layer to fit the application
727  needs */
728 
729 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
730  packet */
731 #ifndef ETH_TX_BUF_SIZE
732  #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
733 #endif
734 
735 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
736 #ifndef ETH_TXBUFNB
737  #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
738 #endif
739 
748 /*
749  DMA Tx Descriptor
750  -----------------------------------------------------------------------------------------------
751  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
752  -----------------------------------------------------------------------------------------------
753  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
754  -----------------------------------------------------------------------------------------------
755  TDES2 | Buffer1 Address [31:0] |
756  -----------------------------------------------------------------------------------------------
757  TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
758  -----------------------------------------------------------------------------------------------
759 */
760 
764 #define ETH_DMATXDESC_OWN 0x80000000U
765 #define ETH_DMATXDESC_IC 0x40000000U
766 #define ETH_DMATXDESC_LS 0x20000000U
767 #define ETH_DMATXDESC_FS 0x10000000U
768 #define ETH_DMATXDESC_DC 0x08000000U
769 #define ETH_DMATXDESC_DP 0x04000000U
770 #define ETH_DMATXDESC_TTSE 0x02000000U
771 #define ETH_DMATXDESC_CIC 0x00C00000U
772 #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U
773 #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U
774 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U
775 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U
776 #define ETH_DMATXDESC_TER 0x00200000U
777 #define ETH_DMATXDESC_TCH 0x00100000U
778 #define ETH_DMATXDESC_TTSS 0x00020000U
779 #define ETH_DMATXDESC_IHE 0x00010000U
780 #define ETH_DMATXDESC_ES 0x00008000U
781 #define ETH_DMATXDESC_JT 0x00004000U
782 #define ETH_DMATXDESC_FF 0x00002000U
783 #define ETH_DMATXDESC_PCE 0x00001000U
784 #define ETH_DMATXDESC_LCA 0x00000800U
785 #define ETH_DMATXDESC_NC 0x00000400U
786 #define ETH_DMATXDESC_LCO 0x00000200U
787 #define ETH_DMATXDESC_EC 0x00000100U
788 #define ETH_DMATXDESC_VF 0x00000080U
789 #define ETH_DMATXDESC_CC 0x00000078U
790 #define ETH_DMATXDESC_ED 0x00000004U
791 #define ETH_DMATXDESC_UF 0x00000002U
792 #define ETH_DMATXDESC_DB 0x00000001U
797 #define ETH_DMATXDESC_TBS2 0x1FFF0000U
798 #define ETH_DMATXDESC_TBS1 0x00001FFFU
803 #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU
808 #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU
810  /*---------------------------------------------------------------------------------------------
811  TDES6 | Transmit Time Stamp Low [31:0] |
812  -----------------------------------------------------------------------------------------------
813  TDES7 | Transmit Time Stamp High [31:0] |
814  ----------------------------------------------------------------------------------------------*/
815 
816 /* Bit definition of TDES6 register */
817  #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */
818 
819 /* Bit definition of TDES7 register */
820  #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */
821 
829 /*
830  DMA Rx Descriptor
831  --------------------------------------------------------------------------------------------------------------------
832  RDES0 | OWN(31) | Status [30:0] |
833  ---------------------------------------------------------------------------------------------------------------------
834  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
835  ---------------------------------------------------------------------------------------------------------------------
836  RDES2 | Buffer1 Address [31:0] |
837  ---------------------------------------------------------------------------------------------------------------------
838  RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
839  ---------------------------------------------------------------------------------------------------------------------
840 */
841 
845 #define ETH_DMARXDESC_OWN 0x80000000U
846 #define ETH_DMARXDESC_AFM 0x40000000U
847 #define ETH_DMARXDESC_FL 0x3FFF0000U
848 #define ETH_DMARXDESC_ES 0x00008000U
849 #define ETH_DMARXDESC_DE 0x00004000U
850 #define ETH_DMARXDESC_SAF 0x00002000U
851 #define ETH_DMARXDESC_LE 0x00001000U
852 #define ETH_DMARXDESC_OE 0x00000800U
853 #define ETH_DMARXDESC_VLAN 0x00000400U
854 #define ETH_DMARXDESC_FS 0x00000200U
855 #define ETH_DMARXDESC_LS 0x00000100U
856 #define ETH_DMARXDESC_IPV4HCE 0x00000080U
857 #define ETH_DMARXDESC_LC 0x00000040U
858 #define ETH_DMARXDESC_FT 0x00000020U
859 #define ETH_DMARXDESC_RWT 0x00000010U
860 #define ETH_DMARXDESC_RE 0x00000008U
861 #define ETH_DMARXDESC_DBE 0x00000004U
862 #define ETH_DMARXDESC_CE 0x00000002U
863 #define ETH_DMARXDESC_MAMPCE 0x00000001U
868 #define ETH_DMARXDESC_DIC 0x80000000U
869 #define ETH_DMARXDESC_RBS2 0x1FFF0000U
870 #define ETH_DMARXDESC_RER 0x00008000U
871 #define ETH_DMARXDESC_RCH 0x00004000U
872 #define ETH_DMARXDESC_RBS1 0x00001FFFU
877 #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU
882 #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU
884 /*---------------------------------------------------------------------------------------------------------------------
885  RDES4 | Reserved[31:15] | Extended Status [14:0] |
886  ---------------------------------------------------------------------------------------------------------------------
887  RDES5 | Reserved[31:0] |
888  ---------------------------------------------------------------------------------------------------------------------
889  RDES6 | Receive Time Stamp Low [31:0] |
890  ---------------------------------------------------------------------------------------------------------------------
891  RDES7 | Receive Time Stamp High [31:0] |
892  --------------------------------------------------------------------------------------------------------------------*/
893 
894 /* Bit definition of RDES4 register */
895 #define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */
896 #define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */
897 #define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */
898  #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */
899  #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */
900  #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */
901  #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */
902  #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
903  #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
904  #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
905 #define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */
906 #define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */
907 #define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */
908 #define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */
909 #define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */
910 #define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */
911  #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */
912  #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */
913  #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */
914 
915 /* Bit definition of RDES6 register */
916 #define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */
917 
918 /* Bit definition of RDES7 register */
919 #define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */
920 
926 #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
927 #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
928 
935 #define ETH_SPEED_10M 0x00000000U
936 #define ETH_SPEED_100M 0x00004000U
937 
944 #define ETH_MODE_FULLDUPLEX 0x00000800U
945 #define ETH_MODE_HALFDUPLEX 0x00000000U
946 
952 #define ETH_RXPOLLING_MODE 0x00000000U
953 #define ETH_RXINTERRUPT_MODE 0x00000001U
954 
961 #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
962 #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
963 
970 #define ETH_MEDIA_INTERFACE_MII 0x00000000U
971 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
972 
979 #define ETH_WATCHDOG_ENABLE 0x00000000U
980 #define ETH_WATCHDOG_DISABLE 0x00800000U
981 
988 #define ETH_JABBER_ENABLE 0x00000000U
989 #define ETH_JABBER_DISABLE 0x00400000U
990 
997 #define ETH_INTERFRAMEGAP_96BIT 0x00000000U
998 #define ETH_INTERFRAMEGAP_88BIT 0x00020000U
999 #define ETH_INTERFRAMEGAP_80BIT 0x00040000U
1000 #define ETH_INTERFRAMEGAP_72BIT 0x00060000U
1001 #define ETH_INTERFRAMEGAP_64BIT 0x00080000U
1002 #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U
1003 #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U
1004 #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U
1012 #define ETH_CARRIERSENCE_ENABLE 0x00000000U
1013 #define ETH_CARRIERSENCE_DISABLE 0x00010000U
1014 
1021 #define ETH_RECEIVEOWN_ENABLE 0x00000000U
1022 #define ETH_RECEIVEOWN_DISABLE 0x00002000U
1023 
1030 #define ETH_LOOPBACKMODE_ENABLE 0x00001000U
1031 #define ETH_LOOPBACKMODE_DISABLE 0x00000000U
1032 
1039 #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
1040 #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
1041 
1048 #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
1049 #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
1050 
1057 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
1058 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
1059 
1066 #define ETH_BACKOFFLIMIT_10 0x00000000U
1067 #define ETH_BACKOFFLIMIT_8 0x00000020U
1068 #define ETH_BACKOFFLIMIT_4 0x00000040U
1069 #define ETH_BACKOFFLIMIT_1 0x00000060U
1070 
1077 #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
1078 #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
1079 
1086 #define ETH_RECEIVEALL_ENABLE 0x80000000U
1087 #define ETH_RECEIVEAll_DISABLE 0x00000000U
1088 
1095 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
1096 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
1097 #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
1098 
1105 #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U
1106 #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U
1107 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U
1115 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
1116 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
1117 
1124 #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
1125 #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
1126 
1133 #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
1134 #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
1135 
1142 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
1143 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
1144 #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
1145 #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
1146 
1153 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
1154 #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
1155 #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
1156 
1163 #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
1164 #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
1165 
1172 #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U
1173 #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U
1174 #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U
1175 #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U
1183 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
1184 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
1185 
1192 #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
1193 #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
1194 
1201 #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
1202 #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
1203 
1210 #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
1211 #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
1212 
1219 #define ETH_MAC_ADDRESS0 0x00000000U
1220 #define ETH_MAC_ADDRESS1 0x00000008U
1221 #define ETH_MAC_ADDRESS2 0x00000010U
1222 #define ETH_MAC_ADDRESS3 0x00000018U
1223 
1230 #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
1231 #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
1232 
1239 #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U
1240 #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U
1241 #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U
1242 #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U
1243 #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U
1244 #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U
1252 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
1253 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
1254 
1261 #define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
1262 #define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
1263 
1270 #define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
1271 #define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
1272 
1279 #define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
1280 #define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
1281 
1288 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U
1289 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U
1290 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U
1291 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U
1292 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U
1293 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U
1294 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U
1295 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U
1303 #define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
1304 #define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
1305 
1312 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
1313 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
1314 
1321 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U
1322 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U
1323 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U
1324 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U
1332 #define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
1333 #define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
1334 
1341 #define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
1342 #define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
1343 
1350 #define ETH_FIXEDBURST_ENABLE 0x00010000U
1351 #define ETH_FIXEDBURST_DISABLE 0x00000000U
1352 
1359 #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U
1360 #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U
1361 #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U
1362 #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U
1363 #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U
1364 #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U
1365 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U
1366 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U
1367 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U
1368 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U
1369 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U
1370 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U
1378 #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U
1379 #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U
1380 #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U
1381 #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U
1382 #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U
1383 #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U
1384 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U
1385 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U
1386 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U
1387 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U
1388 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U
1389 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U
1397 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U
1398 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U
1399 
1406 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
1407 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
1408 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
1409 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
1410 #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
1411 
1418 #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U
1419 #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U
1427 #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U
1428 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U
1429 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U
1430 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U
1438 #define ETH_DMARXDESC_BUFFER1 0x00000000U
1439 #define ETH_DMARXDESC_BUFFER2 0x00000001U
1447 #define ETH_PMT_FLAG_WUFFRPR 0x80000000U
1448 #define ETH_PMT_FLAG_WUFR 0x00000040U
1449 #define ETH_PMT_FLAG_MPR 0x00000020U
1457 #define ETH_MMC_IT_TGF 0x00200000U
1458 #define ETH_MMC_IT_TGFMSC 0x00008000U
1459 #define ETH_MMC_IT_TGFSC 0x00004000U
1467 #define ETH_MMC_IT_RGUF 0x10020000U
1468 #define ETH_MMC_IT_RFAE 0x10000040U
1469 #define ETH_MMC_IT_RFCE 0x10000020U
1477 #define ETH_MAC_FLAG_TST 0x00000200U
1478 #define ETH_MAC_FLAG_MMCT 0x00000040U
1479 #define ETH_MAC_FLAG_MMCR 0x00000020U
1480 #define ETH_MAC_FLAG_MMC 0x00000010U
1481 #define ETH_MAC_FLAG_PMT 0x00000008U
1489 #define ETH_DMA_FLAG_TST 0x20000000U
1490 #define ETH_DMA_FLAG_PMT 0x10000000U
1491 #define ETH_DMA_FLAG_MMC 0x08000000U
1492 #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U
1493 #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U
1494 #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U
1495 #define ETH_DMA_FLAG_NIS 0x00010000U
1496 #define ETH_DMA_FLAG_AIS 0x00008000U
1497 #define ETH_DMA_FLAG_ER 0x00004000U
1498 #define ETH_DMA_FLAG_FBE 0x00002000U
1499 #define ETH_DMA_FLAG_ET 0x00000400U
1500 #define ETH_DMA_FLAG_RWT 0x00000200U
1501 #define ETH_DMA_FLAG_RPS 0x00000100U
1502 #define ETH_DMA_FLAG_RBU 0x00000080U
1503 #define ETH_DMA_FLAG_R 0x00000040U
1504 #define ETH_DMA_FLAG_TU 0x00000020U
1505 #define ETH_DMA_FLAG_RO 0x00000010U
1506 #define ETH_DMA_FLAG_TJT 0x00000008U
1507 #define ETH_DMA_FLAG_TBU 0x00000004U
1508 #define ETH_DMA_FLAG_TPS 0x00000002U
1509 #define ETH_DMA_FLAG_T 0x00000001U
1517 #define ETH_MAC_IT_TST 0x00000200U
1518 #define ETH_MAC_IT_MMCT 0x00000040U
1519 #define ETH_MAC_IT_MMCR 0x00000020U
1520 #define ETH_MAC_IT_MMC 0x00000010U
1521 #define ETH_MAC_IT_PMT 0x00000008U
1529 #define ETH_DMA_IT_TST 0x20000000U
1530 #define ETH_DMA_IT_PMT 0x10000000U
1531 #define ETH_DMA_IT_MMC 0x08000000U
1532 #define ETH_DMA_IT_NIS 0x00010000U
1533 #define ETH_DMA_IT_AIS 0x00008000U
1534 #define ETH_DMA_IT_ER 0x00004000U
1535 #define ETH_DMA_IT_FBE 0x00002000U
1536 #define ETH_DMA_IT_ET 0x00000400U
1537 #define ETH_DMA_IT_RWT 0x00000200U
1538 #define ETH_DMA_IT_RPS 0x00000100U
1539 #define ETH_DMA_IT_RBU 0x00000080U
1540 #define ETH_DMA_IT_R 0x00000040U
1541 #define ETH_DMA_IT_TU 0x00000020U
1542 #define ETH_DMA_IT_RO 0x00000010U
1543 #define ETH_DMA_IT_TJT 0x00000008U
1544 #define ETH_DMA_IT_TBU 0x00000004U
1545 #define ETH_DMA_IT_TPS 0x00000002U
1546 #define ETH_DMA_IT_T 0x00000001U
1554 #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U
1555 #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U
1556 #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U
1557 #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U
1558 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U
1559 #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U
1569 #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U
1570 #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U
1571 #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U
1572 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U
1573 #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U
1574 #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U
1583 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U
1584 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U
1592 #define ETH_EXTI_LINE_WAKEUP 0x00080000U
1602 /* Exported macro ------------------------------------------------------------*/
1603 
1612 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1613 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
1614  (__HANDLE__)->State = HAL_ETH_STATE_RESET; \
1615  (__HANDLE__)->MspInitCallback = NULL; \
1616  (__HANDLE__)->MspDeInitCallback = NULL; \
1617  } while(0)
1618 #else
1619 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
1620 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
1621 
1628 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
1629 
1636 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
1637 
1643 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
1644 
1650 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
1651 
1657 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
1658 
1664 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
1665 
1671 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
1672 
1678 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
1679 
1685 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
1686 
1698 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
1699 
1705 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
1706 
1712 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
1713 
1719 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
1720 
1726 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
1727 
1738 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
1739 
1750 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
1751 
1757 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1758 
1764 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
1765 
1771 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
1772 
1778 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
1779 
1792 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
1793 
1801 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
1802 
1810 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
1811 
1818 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
1819 
1826 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
1827 
1834 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
1835 
1845 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
1846 
1853 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
1854 
1861 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
1862 
1869 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
1870 
1876 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
1877 
1883 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1884 
1890 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
1891 
1897 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
1898 
1904 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
1905 
1911 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
1912 
1923 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
1924 
1930 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
1931 
1937 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
1938  (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
1939 
1945 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
1946 
1952 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
1953 
1959 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
1960 
1966 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
1967 
1973 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
1974 
1980 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
1981 
1987 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
1988 
1999 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
2000 
2010 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
2011 
2021 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
2022 
2033 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
2034 
2039 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
2040 
2045 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
2046 
2051 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
2052 
2057 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
2058 
2063 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
2064 
2069 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
2070 
2075 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
2076 
2081 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2082 
2087 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
2088 
2093 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
2094 
2099 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
2100  EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
2101  }while(0U)
2102 
2107 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2108  EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
2109  }while(0U)
2110 
2115 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
2116 
2120 /* Exported functions --------------------------------------------------------*/
2121 
2126 /* Initialization and de-initialization functions ****************************/
2127 
2131 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
2132 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
2133 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
2134 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
2135 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
2136 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
2137 /* Callbacks Register/UnRegister functions ***********************************/
2138 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
2139 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
2140 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
2141 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
2142 
2146 /* IO operation functions ****************************************************/
2147 
2151 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
2152 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
2153 /* Communication with PHY functions*/
2154 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
2155 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
2156 /* Non-Blocking mode: Interrupt */
2157 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
2158 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
2159 /* Callback in non blocking modes (Interrupt) */
2160 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
2161 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
2162 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
2167 /* Peripheral Control functions **********************************************/
2168 
2173 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
2174 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
2175 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
2176 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
2181 /* Peripheral State functions ************************************************/
2182 
2186 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
2203 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
2204  STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
2205 
2206 #ifdef __cplusplus
2207 }
2208 #endif
2209 
2210 #endif /* __STM32F4xx_HAL_ETH_H */
2211 
2212 
2213 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
Init
napi_value Init(napi_env env, napi_value exports)
Definition: porcupine/demo/c/pvrecorder/node/pv_recorder_napi.c:197
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:51
ETH_TypeDef
Ethernet MAC.
Definition: stm32f407xx.h:368

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:14:52