evkbimxrt1050_flexspi_nor_config.c
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1 /*
2  * Copyright 2017 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
9 
10 /* Component ID definition, used by tools. */
11 #ifndef FSL_COMPONENT_ID
12 #define FSL_COMPONENT_ID "platform.drivers.xip_board"
13 #endif
14 
15 /*******************************************************************************
16  * Code
17  ******************************************************************************/
18 #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
19 #if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
20 __attribute__((section(".boot_hdr.conf")))
21 #elif defined(__ICCARM__)
22 #pragma location = ".boot_hdr.conf"
23 #endif
24 
25 const flexspi_nor_config_t hyperflash_config = {
26  .memConfig =
27  {
29  .version = FLEXSPI_CFG_BLK_VERSION,
31  .csHoldTime = 3u,
32  .csSetupTime = 3u,
33  .columnAddressWidth = 3u,
34  // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
35  .controllerMiscOption =
38  .sflashPadType = kSerialFlash_8Pads,
39  .serialClkFreq = kFlexSpiSerialClk_133MHz,
40  .sflashA1Size = 64u * 1024u * 1024u,
41  .dataValidTime = {16u, 16u},
42  .lookupTable =
43  {
44  // Read LUTs
48  },
49  },
50  .pageSize = 512u,
51  .sectorSize = 256u * 1024u,
52  .blockSize = 256u * 1024u,
53  .isUniformBlockSize = true,
54 };
55 #endif /* XIP_BOOT_HEADER_ENABLE */
CMD_DDR
#define CMD_DDR
Definition: evkbimxrt1050_flexspi_nor_config.h:42
kFlexSpiMiscOffset_WordAddressableEnable
@ kFlexSpiMiscOffset_WordAddressableEnable
Bit for Word Addressable enable.
Definition: evkbimxrt1050_flexspi_nor_config.h:114
CADDR_DDR
#define CADDR_DDR
Definition: evkbimxrt1050_flexspi_nor_config.h:46
kFlexSpiSerialClk_133MHz
@ kFlexSpiSerialClk_133MHz
Definition: evkbimxrt1050_flexspi_nor_config.h:88
DUMMY_DDR
#define DUMMY_DDR
Definition: evkbimxrt1050_flexspi_nor_config.h:64
evkbimxrt1050_flexspi_nor_config.h
READ_DDR
#define READ_DDR
Definition: evkbimxrt1050_flexspi_nor_config.h:58
kFlexSpiMiscOffset_DdrModeEnable
@ kFlexSpiMiscOffset_DdrModeEnable
Bit for DDR clock confiuration indication.
Definition: evkbimxrt1050_flexspi_nor_config.h:117
FLEXSPI_8PAD
#define FLEXSPI_8PAD
Definition: evkbimxrt1050_flexspi_nor_config.h:73
kSerialFlash_8Pads
@ kSerialFlash_8Pads
Definition: evkbimxrt1050_flexspi_nor_config.h:136
RADDR_DDR
#define RADDR_DDR
Definition: evkbimxrt1050_flexspi_nor_config.h:44
STOP
#define STOP
Definition: evkbimxrt1050_flexspi_nor_config.h:68
_flexspi_nor_config::memConfig
flexspi_mem_config_t memConfig
Common memory configuration info via FlexSPI.
Definition: evkbimxrt1050_flexspi_nor_config.h:247
FLEXSPI_1PAD
#define FLEXSPI_1PAD
Definition: evkbimxrt1050_flexspi_nor_config.h:70
FLEXSPI_CFG_BLK_VERSION
#define FLEXSPI_CFG_BLK_VERSION
Definition: evkbimxrt1050_flexspi_nor_config.h:24
kFlexSPIReadSampleClk_ExternalInputFromDqsPad
@ kFlexSPIReadSampleClk_ExternalInputFromDqsPad
Definition: evkbimxrt1050_flexspi_nor_config.h:105
FLEXSPI_CFG_BLK_TAG
#define FLEXSPI_CFG_BLK_TAG
Definition: evkbimxrt1050_flexspi_nor_config.h:23
__attribute__
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
Reverse byte order (16 bit)
Definition: imxrt1050/imxrt1050-evkb/CMSIS/cmsis_armcc.h:492
FLEXSPI_LUT_SEQ
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)
Definition: evkbimxrt1050_flexspi_nor_config.h:75
kFlexSpiMiscOffset_SafeConfigFreqEnable
@ kFlexSpiMiscOffset_SafeConfigFreqEnable
Bit for Safe Configuration Frequency enable.
Definition: evkbimxrt1050_flexspi_nor_config.h:115
_FlexSPIConfig::tag
uint32_t tag
[0x000-0x003] Tag, fixed value 0x42464346UL
Definition: evkbimxrt1050_flexspi_nor_config.h:161
_flexspi_nor_config
Definition: evkbimxrt1050_flexspi_nor_config.h:245
kFlexSpiMiscOffset_DiffClkEnable
@ kFlexSpiMiscOffset_DiffClkEnable
Bit for Differential clock enable.
Definition: evkbimxrt1050_flexspi_nor_config.h:111


picovoice_driver
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autogenerated on Fri Apr 1 2022 02:13:55